SPI_DEVICE/2P Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: 29d22a60a2

Branch: os_regression_2024_10_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	10.295m	63.271ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.040s	42.157us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.900s	192.167us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	41.910s	7.219ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	28.730s	327.542us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.480s	162.394us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.900s	192.167us	20	20	100.00
		spi_device_csr_aliasing	28.730s	327.542us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.050s	13.676us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.030s	72.626us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.280s	64.606us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.730s	98.983us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	1.180s	25.638us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	8.520s	232.997us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.520s	232.997us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	33.250s	10.056ms	50	50	100.00
		spi_device_tpm_sts_read	1.690s	199.011us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.082m	52.698ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	35.280s	60.732ms	50	50	100.00
		spi_device_flash_all	7.280m	54.649ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	50.520s	23.491ms	50	50	100.00
		spi_device_flash_all	7.280m	54.649ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	50.520s	23.491ms	50	50	100.00
		spi_device_flash_all	7.280m	54.649ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.280m	54.649ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	41.060s	38.168ms	50	50	100.00
		spi_device_flash_all	7.280m	54.649ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	41.060s	38.168ms	50	50	100.00
		spi_device_flash_all	7.280m	54.649ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	41.060s	38.168ms	50	50	100.00
		spi_device_flash_all	7.280m	54.649ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	41.060s	38.168ms	50	50	100.00
		spi_device_flash_all	7.280m	54.649ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	41.060s	38.168ms	50	50	100.00
		spi_device_flash_all	7.280m	54.649ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	45.920s	17.092ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.504m	58.271ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.504m	58.271ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.504m	58.271ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.094m	3.969ms	50	50	100.00
		spi_device_read_buffer_direct	26.450s	8.460ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.504m	58.271ms	50	50	100.00
		spi_device_flash_all	7.280m	54.649ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.280m	54.649ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.280m	54.649ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	28.010s	3.349ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	28.010s	3.349ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.295m	63.271ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.539m	242.301ms	50	50	100.00
V2	stress_all	spi_device_stress_all	32.874m	337.055ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.190s	22.593us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.210s	31.710us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	7.990s	5.028ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	7.990s	5.028ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.040s	42.157us	5	5	100.00
		spi_device_csr_rw	3.900s	192.167us	20	20	100.00
		spi_device_csr_aliasing	28.730s	327.542us	5	5	100.00
		spi_device_same_csr_outstanding	6.050s	834.298us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.040s	42.157us	5	5	100.00
		spi_device_csr_rw	3.900s	192.167us	20	20	100.00
		spi_device_csr_aliasing	28.730s	327.542us	5	5	100.00
		spi_device_same_csr_outstanding	6.050s	834.298us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	2.020s	159.472us	5	5	100.00
		spi_device_tl_intg_err	31.040s	2.179ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	31.040s	2.179ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	5.809m	43.799ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.77	98.70	96.92	99.01	89.36	98.59	95.56	99.26

Past Results

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