SPI_DEVICE/2P Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: `1cb1c3d135`

Branch: os_regression_2024_10_02

Simulator: VCS

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	17.003m	194.245ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.220s	41.870us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.990s	1.732ms	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	45.630s	532.842us	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	22.960s	315.565us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.120s	512.036us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.990s	1.732ms	20	20	100.00
		spi_device_csr_aliasing	22.960s	315.565us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.130s	34.297us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.850s	204.322us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.440s	56.362us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.810s	52.871us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	1.080s	19.736us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	12.640s	1.337ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	12.640s	1.337ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	21.670s	22.087ms	50	50	100.00
		spi_device_tpm_sts_read	2.100s	135.820us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.027m	14.005ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	38.450s	5.663ms	50	50	100.00
		spi_device_flash_all	9.312m	75.383ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	33.720s	34.900ms	50	50	100.00
		spi_device_flash_all	9.312m	75.383ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	33.720s	34.900ms	50	50	100.00
		spi_device_flash_all	9.312m	75.383ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.312m	75.383ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	41.280s	6.618ms	50	50	100.00
		spi_device_flash_all	9.312m	75.383ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	41.280s	6.618ms	50	50	100.00
		spi_device_flash_all	9.312m	75.383ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	41.280s	6.618ms	50	50	100.00
		spi_device_flash_all	9.312m	75.383ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	41.280s	6.618ms	50	50	100.00
		spi_device_flash_all	9.312m	75.383ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	41.280s	6.618ms	50	50	100.00
		spi_device_flash_all	9.312m	75.383ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	43.940s	7.522ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.825m	8.156ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.825m	8.156ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.825m	8.156ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.261m	26.298ms	50	50	100.00
		spi_device_read_buffer_direct	31.950s	9.068ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.825m	8.156ms	50	50	100.00
		spi_device_flash_all	9.312m	75.383ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.312m	75.383ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.312m	75.383ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	44.120s	6.180ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	44.120s	6.180ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	17.003m	194.245ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	17.546m	100.425ms	50	50	100.00
V2	stress_all	spi_device_stress_all	18.508m	1.869s	50	50	100.00
V2	alert_test	spi_device_alert_test	1.320s	14.477us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.230s	40.833us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	7.960s	402.731us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	7.960s	402.731us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.220s	41.870us	5	5	100.00
		spi_device_csr_rw	3.990s	1.732ms	20	20	100.00
		spi_device_csr_aliasing	22.960s	315.565us	5	5	100.00
		spi_device_same_csr_outstanding	5.850s	184.092us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.220s	41.870us	5	5	100.00
		spi_device_csr_rw	3.990s	1.732ms	20	20	100.00
		spi_device_csr_aliasing	22.960s	315.565us	5	5	100.00
		spi_device_same_csr_outstanding	5.850s	184.092us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.990s	94.181us	5	5	100.00
		spi_device_tl_intg_err	25.900s	5.873ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	25.900s	5.873ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	8.799m	257.577ms	49	50	98.00
		TOTAL			1150	1151	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.08	98.44	94.08	98.62	89.36	97.27	95.56	99.26

Failure Buckets

UVM_ERROR (spi_device_pass_base_vseq.sv:704) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be *

has 1 failures:

Test spi_device_flash_mode_ignore_cmds has 1 failures.

9.spi_device_flash_mode_ignore_cmds.23060458789978200689814143886846606129215111718231821641468186713067247504305
Line 71, in log /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/9.spi_device_flash_mode_ignore_cmds/latest/run.log

  UVM_ERROR @ 58082987281 ps: (spi_device_pass_base_vseq.sv:704) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  tl_ul_fuzzy_flash_status_q[i] = 0x4dba40
  tl_ul_fuzzy_flash_status_q[i] = 0x546a60
  tl_ul_fuzzy_flash_status_q[i] = 0x546a60
  UVM_INFO @ 63654253256 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 1/3