SPI_HOST Simulation Results

Sunday May 21 2023 07:04:58 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 3002339765

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.733m	98.615ms	47	50	94.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	21.890us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	165.010us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	179.019us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	17.044us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	101.220us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	165.010us	20	20	100.00
		spi_host_csr_aliasing	3.000s	17.044us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	42.237us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	43.996us	5	5	100.00
V1		TOTAL			112	115	97.39
V2	performance	spi_host_performance	6.000s	33.374us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.600m	10.236ms	50	50	100.00
		spi_host_error_cmd	4.000s	15.652us	50	50	100.00
		spi_host_event	22.750m	31.520ms	50	50	100.00
V2	clock_rate	spi_host_speed	8.067m	10.097ms	49	50	98.00
V2	speed	spi_host_speed	8.067m	10.097ms	49	50	98.00
V2	chip_select_timing	spi_host_speed	8.067m	10.097ms	49	50	98.00
V2	sw_reset	spi_host_sw_reset	2.517m	10.001ms	44	50	88.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	127.794us	50	50	100.00
V2	cpol_cpha	spi_host_speed	8.067m	10.097ms	49	50	98.00
V2	full_cycle	spi_host_speed	8.067m	10.097ms	49	50	98.00
V2	duplex	spi_host_smoke	10.733m	98.615ms	47	50	94.00
V2	tx_rx_only	spi_host_smoke	10.733m	98.615ms	47	50	94.00
V2	stress_all	spi_host_stress_all	3.967m	5.219ms	48	50	96.00
V2	spien	spi_host_spien	6.117m	72.220ms	50	50	100.00
V2	stall	spi_host_status_stall	13.417m	38.324ms	47	50	94.00
V2	Idlecsbactive	spi_host_idlecsbactive	1.250m	1.717ms	50	50	100.00
V2	alert_test	spi_host_alert_test	4.000s	19.401us	50	50	100.00
V2	intr_test	spi_host_intr_test	4.000s	46.285us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	166.932us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	166.932us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	21.890us	5	5	100.00
		spi_host_csr_rw	4.000s	165.010us	20	20	100.00
		spi_host_csr_aliasing	3.000s	17.044us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	51.685us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	21.890us	5	5	100.00
		spi_host_csr_rw	4.000s	165.010us	20	20	100.00
		spi_host_csr_aliasing	3.000s	17.044us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	51.685us	20	20	100.00
V2		TOTAL			678	690	98.26
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	145.238us	20	20	100.00
		spi_host_sec_cm	3.000s	89.732us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	145.238us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			815	830	98.19

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	15	15	11	73.33
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.10	98.28	96.18	99.74	96.07	95.70	100.00	98.60	91.29

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 6 failures:

Test spi_host_stress_all has 1 failures.

2.spi_host_stress_all.2962912228
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_stress_all/latest/run.log

  UVM_FATAL @ 10165951736 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xaa5aa714) == 0x0
  UVM_INFO @ 10165951736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_host_sw_reset has 5 failures.

10.spi_host_sw_reset.2457909872
Line 269, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 26416857363 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x19545214) == 0x0
  UVM_INFO @ 26416857363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.spi_host_sw_reset.3284103511
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 10001068186 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xd59f7c94) == 0x0
  UVM_INFO @ 10001068186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 3 failures:

Test spi_host_stress_all has 1 failures.

1.spi_host_stress_all.1842477017
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_stress_all/latest/run.log

  UVM_FATAL @ 23146276400 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x589384d4) == 0x0
  UVM_INFO @ 23146276400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_host_smoke has 1 failures.

26.spi_host_smoke.2197811119
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/26.spi_host_smoke/latest/run.log

  UVM_FATAL @ 180563366054 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x80a66e94) == 0x0
  UVM_INFO @ 180563366054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_host_speed has 1 failures.

47.spi_host_speed.3642598894
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/47.spi_host_speed/latest/run.log

  UVM_FATAL @ 79742060883 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x926be9d4) == 0x0
  UVM_INFO @ 79742060883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

Test spi_host_status_stall has 2 failures.

7.spi_host_status_stall.1812486609
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_status_stall/latest/run.log

  UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

31.spi_host_status_stall.1494697230
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_status_stall/latest/run.log

  UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test spi_host_smoke has 1 failures.
  - 10.spi_host_smoke.2400956143
    Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_status_stall has 1 failures.
  - 22.spi_host_status_stall.2972636327
    Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
- Test spi_host_smoke has 1 failures.
  - 13.spi_host_smoke.2672100646
    Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 120164101885 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xf534ac14) == 0x0
  UVM_INFO @ 120164101885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
- Test spi_host_sw_reset has 1 failures.
  - 28.spi_host_sw_reset.1787254064
    Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_sw_reset/latest/run.log
```
  UVM_FATAL @ 10003585936 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x1b4a7794) == 0x0
  UVM_INFO @ 10003585936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```