df66f8a42e| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 10.567m | 52.400ms | 45 | 50 | 90.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 2.000s | 17.821us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 7.000s | 64.428us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 8.000s | 38.189us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 4.000s | 23.263us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 4.000s | 241.519us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 7.000s | 64.428us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 4.000s | 23.263us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 2.000s | 26.592us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 48.504us | 5 | 5 | 100.00 |
| V1 | TOTAL | 110 | 115 | 95.65 | |||
| V2 | performance | spi_host_performance | 9.000s | 31.774us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 3.567m | 17.171ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 7.000s | 43.470us | 50 | 50 | 100.00 | ||
| spi_host_event | 24.767m | 32.579ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 6.400m | 7.937ms | 49 | 50 | 98.00 |
| V2 | speed | spi_host_speed | 6.400m | 7.937ms | 49 | 50 | 98.00 |
| V2 | chip_select_timing | spi_host_speed | 6.400m | 7.937ms | 49 | 50 | 98.00 |
| V2 | sw_reset | spi_host_sw_reset | 8.300m | 28.504ms | 50 | 50 | 100.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 8.000s | 1.097ms | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 6.400m | 7.937ms | 49 | 50 | 98.00 |
| V2 | full_cycle | spi_host_speed | 6.400m | 7.937ms | 49 | 50 | 98.00 |
| V2 | duplex | spi_host_smoke | 10.567m | 52.400ms | 45 | 50 | 90.00 |
| V2 | tx_rx_only | spi_host_smoke | 10.567m | 52.400ms | 45 | 50 | 90.00 |
| V2 | stress_all | spi_host_stress_all | 3.417m | 13.490ms | 49 | 50 | 98.00 |
| V2 | spien | spi_host_spien | 7.017m | 85.367ms | 50 | 50 | 100.00 |
| V2 | stall | spi_host_status_stall | 9.817m | 13.532ms | 44 | 50 | 88.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 52.000s | 5.972ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 6.000s | 40.339us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 4.000s | 17.067us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 9.000s | 113.115us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 9.000s | 113.115us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 2.000s | 17.821us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 7.000s | 64.428us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 4.000s | 23.263us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 8.000s | 192.570us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 2.000s | 17.821us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 7.000s | 64.428us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 4.000s | 23.263us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 8.000s | 192.570us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 682 | 690 | 98.84 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 8.000s | 171.050us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 2.000s | 366.873us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 8.000s | 171.050us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 817 | 830 | 98.43 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 15 | 15 | 12 | 80.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.08 | 98.13 | 95.98 | 99.73 | 96.70 | 95.70 | 100.00 | 98.60 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 9 failures:
Test spi_host_smoke has 4 failures.
2.spi_host_smoke.21238713122700306492544342186009195909209485586339005777402129165268500128388
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_smoke/latest/run.log
UVM_FATAL @ 94267806135 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xad37e694) == 0x0
UVM_INFO @ 94267806135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.spi_host_smoke.71403252040442914180316516251143150744204148691089135530502337795726683227123
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_smoke/latest/run.log
UVM_FATAL @ 114432548739 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x8b18f614) == 0x0
UVM_INFO @ 114432548739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_host_status_stall has 3 failures.
7.spi_host_status_stall.96518878241093967753710736164059152023684235592077098942331045307655592207864
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_status_stall/latest/run.log
UVM_FATAL @ 195708680854 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x69a40e54) == 0x0
UVM_INFO @ 195708680854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.spi_host_status_stall.88219943564409668860678602922209534173327944350567028800468530726182551899729
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_status_stall/latest/run.log
UVM_FATAL @ 207814070807 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x96a63f54) == 0x0
UVM_INFO @ 207814070807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_stress_all has 1 failures.
32.spi_host_stress_all.20197279975973005013925452929321177982522599751419147249269592947053568387954
Line 280, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15434542866 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xf7188754) == 0x0
UVM_INFO @ 15434542866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_speed has 1 failures.
35.spi_host_speed.57165750728572106901362644693377978350512605649946770975902611496779855013491
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/35.spi_host_speed/latest/run.log
UVM_FATAL @ 62936031343 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x5ad7c754) == 0x0
UVM_INFO @ 62936031343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
33.spi_host_status_stall.104530138924793293781275873366692449629103956485040363424366198736314810847181
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_status_stall/latest/run.log
UVM_FATAL @ 26300908768 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x2f719554) == 0x1
UVM_INFO @ 26300908768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
40.spi_host_smoke.66842180320750146165621920486439339835810304426688938398176737496296697471290
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/40.spi_host_smoke/latest/run.log
UVM_FATAL @ 87040925784 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x975f4ed4) == 0x0
UVM_INFO @ 87040925784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
44.spi_host_status_stall.94610329251334261841244316598631109954223724026182600642279867257079506632324
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/44.spi_host_status_stall/latest/run.log
UVM_FATAL @ 33607145644 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x5dfc13d4) == 0x1
UVM_INFO @ 33607145644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:464) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.status.rxfull reset value: * has 1 failures:
47.spi_host_status_stall.25229815431124110526852964131629415342810633655697132750626402784766862530101
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/47.spi_host_status_stall/latest/run.log
UVM_ERROR @ 2391929368 ps: (csr_utils_pkg.sv:464) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.status.rxfull reset value: 0x0
UVM_INFO @ 2391929368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---