d09e282b26| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 8.033m | 10.008ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 3.000s | 36.071us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 7.000s | 47.281us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5.000s | 203.207us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 8.000s | 214.474us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 7.000s | 111.802us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 7.000s | 47.281us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 8.000s | 214.474us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 2.000s | 43.113us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 12.000s | 43.243us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | performance | spi_host_performance | 13.000s | 88.425us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 2.617m | 12.973ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 7.000s | 45.406us | 50 | 50 | 100.00 | ||
| spi_host_event | 11.767m | 16.497ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 25.000s | 1.928ms | 50 | 50 | 100.00 |
| V2 | speed | spi_host_speed | 25.000s | 1.928ms | 50 | 50 | 100.00 |
| V2 | chip_select_timing | spi_host_speed | 25.000s | 1.928ms | 50 | 50 | 100.00 |
| V2 | sw_reset | spi_host_sw_reset | 5.333m | 21.860ms | 50 | 50 | 100.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 7.000s | 301.650us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 25.000s | 1.928ms | 50 | 50 | 100.00 |
| V2 | full_cycle | spi_host_speed | 25.000s | 1.928ms | 50 | 50 | 100.00 |
| V2 | duplex | spi_host_smoke | 8.033m | 10.008ms | 50 | 50 | 100.00 |
| V2 | tx_rx_only | spi_host_smoke | 8.033m | 10.008ms | 50 | 50 | 100.00 |
| V2 | stress_all | spi_host_stress_all | 1.967m | 2.482ms | 50 | 50 | 100.00 |
| V2 | spien | spi_host_spien | 5.783m | 15.122ms | 50 | 50 | 100.00 |
| V2 | stall | spi_host_status_stall | 8.200m | 10.509ms | 47 | 50 | 94.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 29.000s | 983.704us | 50 | 50 | 100.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 2.617m | 12.973ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 8.000s | 53.192us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 7.000s | 35.189us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 9.000s | 101.709us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 9.000s | 101.709us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 3.000s | 36.071us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 7.000s | 47.281us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 8.000s | 214.474us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 7.000s | 105.106us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 3.000s | 36.071us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 7.000s | 47.281us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 8.000s | 214.474us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 7.000s | 105.106us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 687 | 690 | 99.57 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 17.000s | 59.957us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 7.000s | 75.848us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 17.000s | 59.957us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | spi_host_upper_range_clkdiv | 53.067m | 100.003ms | 3 | 10 | 30.00 | |
| TOTAL | 830 | 840 | 98.81 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 15 | 15 | 14 | 93.33 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 91.01 | 90.92 | 83.18 | 92.77 | 89.84 | 95.70 | 100.00 | 95.07 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 3 failures:
1.spi_host_upper_range_clkdiv.27875827807063544289786197423931074505473646406732967352007017130517514571813
Line 337, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100001785519 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x94bb5314, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100001785519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.spi_host_upper_range_clkdiv.53872620363658456647305115954627560168375625946490004584123275231554627861751
Line 330, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100005318519 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xefbf5854, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100005318519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 3 failures:
3.spi_host_upper_range_clkdiv.58755028175343206873556018651950351481772168346906780399040988031342160166584
Line 342, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100002735794 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x63c3de94, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100002735794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.spi_host_upper_range_clkdiv.30779476093067636651141799917446947207276419877624397597864007236973022088722
Line 329, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003913752 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x21421354, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100003913752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=79) has 1 failures:
1.spi_host_status_stall.29506293790067764091705145714877938744031677186939175542708786936057785427505
Line 870, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10597659171 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa8a4c514, Comparison=CompareOpEq, exp_data=0x1, call_count=79)
UVM_INFO @ 10597659171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
2.spi_host_upper_range_clkdiv.51047999843810244841250456777005648909396662805655639140167433645800165192454
Line 351, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 140333193739 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x4f183454, Comparison=CompareOpEq, exp_data=0x0, call_count=16)
UVM_INFO @ 140333193739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=83) has 1 failures:
20.spi_host_status_stall.90441362694622216585640166236469203526035811450817535692266051495427716594007
Line 899, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10508590354 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x8b2e4054, Comparison=CompareOpEq, exp_data=0x1, call_count=83)
UVM_INFO @ 10508590354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=80) has 1 failures:
49.spi_host_status_stall.55405589155896140001088537474473547969066003287452864550450789315653841907646
Line 909, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/49.spi_host_status_stall/latest/run.log
UVM_FATAL @ 21444836493 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xc5e56354, Comparison=CompareOpEq, exp_data=0x1, call_count=80)
UVM_INFO @ 21444836493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---