SPI_HOST Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 9.667m 25.579ms 50 50 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 2.000s 16.907us 5 5 100.00
V1 csr_rw spi_host_csr_rw 7.000s 23.066us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 457.095us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 2.000s 105.683us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 7.000s 24.501us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 7.000s 23.066us 20 20 100.00
spi_host_csr_aliasing 2.000s 105.683us 5 5 100.00
V1 mem_walk spi_host_mem_walk 6.000s 14.364us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 18.748us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 performance spi_host_performance 7.000s 35.008us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 1.533m 1.940ms 50 50 100.00
spi_host_error_cmd 3.000s 16.910us 50 50 100.00
spi_host_event 21.333m 35.994ms 50 50 100.00
V2 clock_rate spi_host_speed 35.000s 10.085ms 48 50 96.00
V2 speed spi_host_speed 35.000s 10.085ms 48 50 96.00
V2 chip_select_timing spi_host_speed 35.000s 10.085ms 48 50 96.00
V2 sw_reset spi_host_sw_reset 2.233m 4.195ms 49 50 98.00
V2 passthrough_mode spi_host_passthrough_mode 3.000s 148.915us 50 50 100.00
V2 cpol_cpha spi_host_speed 35.000s 10.085ms 48 50 96.00
V2 full_cycle spi_host_speed 35.000s 10.085ms 48 50 96.00
V2 duplex spi_host_smoke 9.667m 25.579ms 50 50 100.00
V2 tx_rx_only spi_host_smoke 9.667m 25.579ms 50 50 100.00
V2 stress_all spi_host_stress_all 4.383m 31.498ms 50 50 100.00
V2 spien spi_host_spien 6.233m 7.863ms 50 50 100.00
V2 stall spi_host_status_stall 8.450m 92.152ms 45 50 90.00
V2 Idlecsbactive spi_host_idlecsbactive 29.000s 2.279ms 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 1.533m 1.940ms 50 50 100.00
V2 alert_test spi_host_alert_test 3.000s 36.600us 50 50 100.00
V2 intr_test spi_host_intr_test 8.000s 25.320us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 10.000s 138.506us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 10.000s 138.506us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 2.000s 16.907us 5 5 100.00
spi_host_csr_rw 7.000s 23.066us 20 20 100.00
spi_host_csr_aliasing 2.000s 105.683us 5 5 100.00
spi_host_same_csr_outstanding 7.000s 23.134us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 2.000s 16.907us 5 5 100.00
spi_host_csr_rw 7.000s 23.066us 20 20 100.00
spi_host_csr_aliasing 2.000s 105.683us 5 5 100.00
spi_host_same_csr_outstanding 7.000s 23.134us 20 20 100.00
V2 TOTAL 682 690 98.84
V2S tl_intg_err spi_host_tl_intg_err 7.000s 74.690us 20 20 100.00
spi_host_sec_cm 3.000s 214.962us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 7.000s 74.690us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 46.133m 93.081ms 3 10 30.00
TOTAL 825 840 98.21

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 8 100.00
V2 15 15 12 80.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.02 90.92 83.18 92.77 89.92 95.70 100.00 95.07 90.87

Failure Buckets

Past Results