07b417ef03| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 9.333m | 73.532ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 3.000s | 51.521us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 3.000s | 36.529us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5.000s | 630.873us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 29.384us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 3.000s | 29.985us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 3.000s | 36.529us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 29.384us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 3.000s | 17.448us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 16.683us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | performance | spi_host_performance | 13.000s | 185.830us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 1.633m | 2.037ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 12.000s | 18.346us | 50 | 50 | 100.00 | ||
| spi_host_event | 7.400m | 41.056ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 31.000s | 3.823ms | 50 | 50 | 100.00 |
| V2 | speed | spi_host_speed | 31.000s | 3.823ms | 50 | 50 | 100.00 |
| V2 | chip_select_timing | spi_host_speed | 31.000s | 3.823ms | 50 | 50 | 100.00 |
| V2 | sw_reset | spi_host_sw_reset | 7.217m | 10.003ms | 47 | 50 | 94.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 8.000s | 962.499us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 31.000s | 3.823ms | 50 | 50 | 100.00 |
| V2 | full_cycle | spi_host_speed | 31.000s | 3.823ms | 50 | 50 | 100.00 |
| V2 | duplex | spi_host_smoke | 9.333m | 73.532ms | 50 | 50 | 100.00 |
| V2 | tx_rx_only | spi_host_smoke | 9.333m | 73.532ms | 50 | 50 | 100.00 |
| V2 | stress_all | spi_host_stress_all | 5.333m | 15.004ms | 48 | 50 | 96.00 |
| V2 | spien | spi_host_spien | 7.983m | 13.678ms | 50 | 50 | 100.00 |
| V2 | stall | spi_host_status_stall | 12.633m | 34.017ms | 45 | 50 | 90.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 56.000s | 11.300ms | 50 | 50 | 100.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 1.633m | 2.037ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 11.000s | 17.380us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 3.000s | 46.415us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 5.000s | 83.939us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 5.000s | 83.939us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 3.000s | 51.521us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 36.529us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 29.384us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 36.300us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 3.000s | 51.521us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 36.529us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 29.384us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 36.300us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 680 | 690 | 98.55 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 3.000s | 314.160us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 4.000s | 45.161us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 3.000s | 314.160us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | spi_host_upper_range_clkdiv | 56.717m | 200.000ms | 3 | 10 | 30.00 | |
| TOTAL | 823 | 840 | 97.98 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 15 | 15 | 12 | 80.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 91.01 | 90.92 | 83.18 | 92.77 | 89.84 | 95.70 | 100.00 | 95.07 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 3 failures:
Test spi_host_upper_range_clkdiv has 2 failures.
7.spi_host_upper_range_clkdiv.106703679628047830759591190949116836843813549681184691575553433940672473510515
Line 327, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100001458134 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x33c2d454, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100001458134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.spi_host_upper_range_clkdiv.64385730197779669172887038863975604952247086807179894864997678977416601822960
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100006205537 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xd4df2b94, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100006205537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_stress_all has 1 failures.
43.spi_host_stress_all.81918795512787636917516978256381168517287061685590477080753584721810688090403
Line 318, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15003522452 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xebc39dd4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15003522452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 2 failures:
1.spi_host_upper_range_clkdiv.102584976494148327831539195629043527927525387061453058740505905467455693788829
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100002300483 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x7e7e2694, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100002300483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.spi_host_upper_range_clkdiv.50842751228389572698772051068497038402522018067315255298942332639527064639283
Line 307, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003670882 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x55776cd4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100003670882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job spi_host-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
0.spi_host_upper_range_clkdiv.42345030394892774335398411295494091374462310810695981396020421078997996137298
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:5b7ba57f-c18b-4963-90eb-9f1e07667188
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
2.spi_host_upper_range_clkdiv.112892110383002815208620423174401591116351563691541619106298829025318085220071
Line 303, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003677251 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x554b8354, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
UVM_INFO @ 100003677251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
2.spi_host_sw_reset.257401934131613329060898858342872585698709021164357493306918736397857883172
Line 318, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10002741139 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf8116c94, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10002741139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
4.spi_host_upper_range_clkdiv.36045458306319349057476832167818860420389049618706212600676744145849380336389
Line 381, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=108) has 1 failures:
5.spi_host_sw_reset.60526591526221445513854076633739961344506485371079437370486254913487097649517
Line 818, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10123240917 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc8f76e14, Comparison=CompareOpEq, exp_data=0x0, call_count=108)
UVM_INFO @ 10123240917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=77) has 1 failures:
15.spi_host_status_stall.108496137241165142828166290210921627439334855859147794865046770608156037394486
Line 867, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10454294182 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa4a71d94, Comparison=CompareOpEq, exp_data=0x1, call_count=77)
UVM_INFO @ 10454294182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=29) has 1 failures:
15.spi_host_stress_all.36362314886413288160253625898549095429422911501806098346305516578716014428669
Line 400, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10178426830 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x8c1a45d4, Comparison=CompareOpEq, exp_data=0x0, call_count=29)
UVM_INFO @ 10178426830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=87) has 1 failures:
18.spi_host_status_stall.35699694220873536786289539305123308113333961486175381330836315670459231584111
Line 919, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10252681359 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xc7307954, Comparison=CompareOpEq, exp_data=0x1, call_count=87)
UVM_INFO @ 10252681359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=77) has 1 failures:
38.spi_host_status_stall.44404748452588036374628794538442028170259342444309011547665176051086982757812
Line 840, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_status_stall/latest/run.log
UVM_FATAL @ 12110400442 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xb2033714, Comparison=CompareOpEq, exp_data=0x1, call_count=77)
UVM_INFO @ 12110400442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
42.spi_host_sw_reset.53392312562819349690564432901097497827508060448691206679909842505355430313463
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/42.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10016952979 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x3cd8ffd4, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
UVM_INFO @ 10016952979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=86) has 1 failures:
43.spi_host_status_stall.86822753266895612767755155338716343375010754396147109899711914317300240883858
Line 920, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_status_stall/latest/run.log
UVM_FATAL @ 28346448770 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x484dc414, Comparison=CompareOpEq, exp_data=0x1, call_count=86)
UVM_INFO @ 28346448770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=92) has 1 failures:
49.spi_host_status_stall.58309757454554513704122013768476527797792390318373229322742009494241791376133
Line 923, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/49.spi_host_status_stall/latest/run.log
UVM_FATAL @ 34016725348 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xe1a5ed54, Comparison=CompareOpEq, exp_data=0x1, call_count=92)
UVM_INFO @ 34016725348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---