SPI_HOST Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: 3707c48f56

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 7.817m 50.043ms 48 50 96.00
V1 csr_hw_reset spi_host_csr_hw_reset 7.000s 51.688us 5 5 100.00
V1 csr_rw spi_host_csr_rw 7.000s 34.066us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 574.846us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 30.297us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 8.000s 118.675us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 7.000s 34.066us 20 20 100.00
spi_host_csr_aliasing 3.000s 30.297us 5 5 100.00
V1 mem_walk spi_host_mem_walk 7.000s 15.420us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 19.108us 5 5 100.00
V1 TOTAL 113 115 98.26
V2 performance spi_host_performance 8.000s 247.272us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.467m 12.321ms 50 50 100.00
spi_host_error_cmd 12.000s 14.990us 50 50 100.00
spi_host_event 22.683m 121.013ms 50 50 100.00
V2 clock_rate spi_host_speed 24.000s 487.278us 50 50 100.00
V2 speed spi_host_speed 24.000s 487.278us 50 50 100.00
V2 chip_select_timing spi_host_speed 24.000s 487.278us 50 50 100.00
V2 sw_reset spi_host_sw_reset 7.833m 22.253ms 49 50 98.00
V2 passthrough_mode spi_host_passthrough_mode 9.000s 282.532us 50 50 100.00
V2 cpol_cpha spi_host_speed 24.000s 487.278us 50 50 100.00
V2 full_cycle spi_host_speed 24.000s 487.278us 50 50 100.00
V2 duplex spi_host_smoke 7.817m 50.043ms 48 50 96.00
V2 tx_rx_only spi_host_smoke 7.817m 50.043ms 48 50 96.00
V2 stress_all spi_host_stress_all 3.650m 43.134ms 50 50 100.00
V2 spien spi_host_spien 5.267m 64.218ms 50 50 100.00
V2 stall spi_host_status_stall 8.467m 43.246ms 47 50 94.00
V2 Idlecsbactive spi_host_idlecsbactive 59.000s 4.766ms 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 2.467m 12.321ms 50 50 100.00
V2 alert_test spi_host_alert_test 12.000s 22.094us 50 50 100.00
V2 intr_test spi_host_intr_test 7.000s 18.383us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 8.000s 35.893us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 8.000s 35.893us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 7.000s 51.688us 5 5 100.00
spi_host_csr_rw 7.000s 34.066us 20 20 100.00
spi_host_csr_aliasing 3.000s 30.297us 5 5 100.00
spi_host_same_csr_outstanding 7.000s 23.744us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 7.000s 51.688us 5 5 100.00
spi_host_csr_rw 7.000s 34.066us 20 20 100.00
spi_host_csr_aliasing 3.000s 30.297us 5 5 100.00
spi_host_same_csr_outstanding 7.000s 23.744us 20 20 100.00
V2 TOTAL 686 690 99.42
V2S tl_intg_err spi_host_tl_intg_err 8.000s 267.852us 20 20 100.00
spi_host_sec_cm 7.000s 36.650us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 8.000s 267.852us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 51.250m 100.003ms 1 10 10.00
TOTAL 825 840 98.21

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 7 87.50
V2 15 15 13 86.67
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.01 90.92 83.18 92.77 89.84 95.70 100.00 95.07 90.87

Failure Buckets

Past Results