SPI_HOST Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: c082b8981f

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 6.550m 16.889ms 50 50 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 7.000s 64.021us 5 5 100.00
V1 csr_rw spi_host_csr_rw 7.000s 153.199us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 828.851us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 110.780us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 10.000s 39.062us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 7.000s 153.199us 20 20 100.00
spi_host_csr_aliasing 3.000s 110.780us 5 5 100.00
V1 mem_walk spi_host_mem_walk 7.000s 20.710us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 17.081us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 performance spi_host_performance 18.000s 39.324us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.467m 3.250ms 50 50 100.00
spi_host_error_cmd 13.000s 31.584us 50 50 100.00
spi_host_event 4.817m 78.838ms 50 50 100.00
V2 clock_rate spi_host_speed 38.000s 3.365ms 50 50 100.00
V2 speed spi_host_speed 38.000s 3.365ms 50 50 100.00
V2 chip_select_timing spi_host_speed 38.000s 3.365ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 14.083m 27.858ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 13.000s 801.746us 50 50 100.00
V2 cpol_cpha spi_host_speed 38.000s 3.365ms 50 50 100.00
V2 full_cycle spi_host_speed 38.000s 3.365ms 50 50 100.00
V2 duplex spi_host_smoke 6.550m 16.889ms 50 50 100.00
V2 tx_rx_only spi_host_smoke 6.550m 16.889ms 50 50 100.00
V2 stress_all spi_host_stress_all 2.850m 5.610ms 50 50 100.00
V2 spien spi_host_spien 4.400m 7.013ms 50 50 100.00
V2 stall spi_host_status_stall 12.533m 16.183ms 43 50 86.00
V2 Idlecsbactive spi_host_idlecsbactive 40.000s 2.912ms 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 2.467m 3.250ms 50 50 100.00
V2 alert_test spi_host_alert_test 12.000s 20.305us 50 50 100.00
V2 intr_test spi_host_intr_test 7.000s 31.501us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 9.000s 77.146us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 9.000s 77.146us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 7.000s 64.021us 5 5 100.00
spi_host_csr_rw 7.000s 153.199us 20 20 100.00
spi_host_csr_aliasing 3.000s 110.780us 5 5 100.00
spi_host_same_csr_outstanding 7.000s 53.266us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 7.000s 64.021us 5 5 100.00
spi_host_csr_rw 7.000s 153.199us 20 20 100.00
spi_host_csr_aliasing 3.000s 110.780us 5 5 100.00
spi_host_same_csr_outstanding 7.000s 53.266us 20 20 100.00
V2 TOTAL 683 690 98.99
V2S tl_intg_err spi_host_tl_intg_err 10.000s 238.429us 20 20 100.00
spi_host_sec_cm 3.000s 57.688us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 10.000s 238.429us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 57.333m 184.729ms 2 10 20.00
TOTAL 825 840 98.21

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 8 100.00
V2 15 15 14 93.33
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.00 90.92 83.18 92.77 89.69 95.70 100.00 95.07 90.87

Failure Buckets

Past Results