SPI_HOST Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 9.267m 22.564ms 49 50 98.00
V1 csr_hw_reset spi_host_csr_hw_reset 2.000s 51.782us 5 5 100.00
V1 csr_rw spi_host_csr_rw 3.000s 62.158us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 1.715ms 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 18.567us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 4.000s 546.487us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 3.000s 62.158us 20 20 100.00
spi_host_csr_aliasing 3.000s 18.567us 5 5 100.00
V1 mem_walk spi_host_mem_walk 3.000s 15.355us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 40.230us 5 5 100.00
V1 TOTAL 114 115 99.13
V2 performance spi_host_performance 8.000s 239.508us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.767m 7.193ms 50 50 100.00
spi_host_error_cmd 12.000s 18.444us 50 50 100.00
spi_host_event 13.867m 84.153ms 50 50 100.00
V2 clock_rate spi_host_speed 30.000s 10.113ms 49 50 98.00
V2 speed spi_host_speed 30.000s 10.113ms 49 50 98.00
V2 chip_select_timing spi_host_speed 30.000s 10.113ms 49 50 98.00
V2 sw_reset spi_host_sw_reset 2.300m 5.817ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 13.000s 182.966us 50 50 100.00
V2 cpol_cpha spi_host_speed 30.000s 10.113ms 49 50 98.00
V2 full_cycle spi_host_speed 30.000s 10.113ms 49 50 98.00
V2 duplex spi_host_smoke 9.267m 22.564ms 49 50 98.00
V2 tx_rx_only spi_host_smoke 9.267m 22.564ms 49 50 98.00
V2 stress_all spi_host_stress_all 2.683m 11.704ms 50 50 100.00
V2 spien spi_host_spien 3.033m 15.561ms 50 50 100.00
V2 stall spi_host_status_stall 6.450m 28.512ms 47 50 94.00
V2 Idlecsbactive spi_host_idlecsbactive 42.000s 5.869ms 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 2.767m 7.193ms 50 50 100.00
V2 alert_test spi_host_alert_test 7.000s 17.416us 50 50 100.00
V2 intr_test spi_host_intr_test 3.000s 16.626us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 5.000s 733.977us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 5.000s 733.977us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 2.000s 51.782us 5 5 100.00
spi_host_csr_rw 3.000s 62.158us 20 20 100.00
spi_host_csr_aliasing 3.000s 18.567us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 35.921us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 2.000s 51.782us 5 5 100.00
spi_host_csr_rw 3.000s 62.158us 20 20 100.00
spi_host_csr_aliasing 3.000s 18.567us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 35.921us 20 20 100.00
V2 TOTAL 686 690 99.42
V2S tl_intg_err spi_host_tl_intg_err 3.000s 176.717us 20 20 100.00
spi_host_sec_cm 3.000s 217.250us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 3.000s 176.717us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 56.500m 146.738ms 6 10 60.00
TOTAL 831 840 98.93

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 7 87.50
V2 15 15 13 86.67
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.01 90.92 83.18 92.77 89.84 95.70 100.00 95.07 90.87

Failure Buckets

Past Results