SPI_HOST Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 7.600m 9.337ms 50 50 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 3.000s 20.781us 5 5 100.00
V1 csr_rw spi_host_csr_rw 7.000s 17.893us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 9.000s 899.607us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 119.988us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 8.000s 35.125us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 7.000s 17.893us 20 20 100.00
spi_host_csr_aliasing 3.000s 119.988us 5 5 100.00
V1 mem_walk spi_host_mem_walk 13.000s 18.030us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 19.690us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 performance spi_host_performance 3.000s 101.819us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.117m 10.360ms 50 50 100.00
spi_host_error_cmd 3.000s 23.638us 50 50 100.00
spi_host_event 22.317m 65.087ms 50 50 100.00
V2 clock_rate spi_host_speed 29.000s 2.163ms 50 50 100.00
V2 speed spi_host_speed 29.000s 2.163ms 50 50 100.00
V2 chip_select_timing spi_host_speed 29.000s 2.163ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 1.083m 1.886ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 3.000s 934.934us 50 50 100.00
V2 cpol_cpha spi_host_speed 29.000s 2.163ms 50 50 100.00
V2 full_cycle spi_host_speed 29.000s 2.163ms 50 50 100.00
V2 duplex spi_host_smoke 7.600m 9.337ms 50 50 100.00
V2 tx_rx_only spi_host_smoke 7.600m 9.337ms 50 50 100.00
V2 stress_all spi_host_stress_all 3.300m 20.697ms 50 50 100.00
V2 spien spi_host_spien 4.750m 9.589ms 50 50 100.00
V2 stall spi_host_status_stall 5.167m 120.524ms 47 50 94.00
V2 Idlecsbactive spi_host_idlecsbactive 59.000s 9.558ms 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 2.117m 10.360ms 50 50 100.00
V2 alert_test spi_host_alert_test 3.000s 38.277us 50 50 100.00
V2 intr_test spi_host_intr_test 12.000s 17.153us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 14.000s 82.222us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 14.000s 82.222us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 3.000s 20.781us 5 5 100.00
spi_host_csr_rw 7.000s 17.893us 20 20 100.00
spi_host_csr_aliasing 3.000s 119.988us 5 5 100.00
spi_host_same_csr_outstanding 7.000s 22.894us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 3.000s 20.781us 5 5 100.00
spi_host_csr_rw 7.000s 17.893us 20 20 100.00
spi_host_csr_aliasing 3.000s 119.988us 5 5 100.00
spi_host_same_csr_outstanding 7.000s 22.894us 20 20 100.00
V2 TOTAL 687 690 99.57
V2S tl_intg_err spi_host_tl_intg_err 8.000s 269.430us 20 20 100.00
spi_host_sec_cm 3.000s 61.207us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 8.000s 269.430us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 53.467m 100.003ms 1 10 10.00
TOTAL 828 840 98.57

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 8 100.00
V2 15 15 14 93.33
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.02 90.92 83.18 92.77 89.92 95.70 100.00 95.07 90.87

Failure Buckets

Past Results