SPI_HOST Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	8.633m	21.365ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	63.299us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	12.000s	32.537us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	8.000s	215.000us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	22.879us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	7.000s	74.688us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	12.000s	32.537us	20	20	100.00
		spi_host_csr_aliasing	3.000s	22.879us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	20.094us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	39.236us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	13.000s	227.252us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	1.983m	8.796ms	50	50	100.00
		spi_host_error_cmd	8.000s	42.660us	50	50	100.00
		spi_host_event	13.500m	77.597ms	50	50	100.00
V2	clock_rate	spi_host_speed	24.000s	484.875us	50	50	100.00
V2	speed	spi_host_speed	24.000s	484.875us	50	50	100.00
V2	chip_select_timing	spi_host_speed	24.000s	484.875us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	7.050m	15.254ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	7.000s	186.441us	50	50	100.00
V2	cpol_cpha	spi_host_speed	24.000s	484.875us	50	50	100.00
V2	full_cycle	spi_host_speed	24.000s	484.875us	50	50	100.00
V2	duplex	spi_host_smoke	8.633m	21.365ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	8.633m	21.365ms	50	50	100.00
V2	stress_all	spi_host_stress_all	2.033m	18.548ms	50	50	100.00
V2	spien	spi_host_spien	4.500m	6.402ms	50	50	100.00
V2	stall	spi_host_status_stall	7.750m	10.356ms	48	50	96.00
V2	Idlecsbactive	spi_host_idlecsbactive	54.000s	4.039ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	1.983m	8.796ms	50	50	100.00
V2	alert_test	spi_host_alert_test	8.000s	40.284us	50	50	100.00
V2	intr_test	spi_host_intr_test	12.000s	61.738us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	279.020us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	279.020us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	63.299us	5	5	100.00
		spi_host_csr_rw	12.000s	32.537us	20	20	100.00
		spi_host_csr_aliasing	3.000s	22.879us	5	5	100.00
		spi_host_same_csr_outstanding	7.000s	62.070us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	63.299us	5	5	100.00
		spi_host_csr_rw	12.000s	32.537us	20	20	100.00
		spi_host_csr_aliasing	3.000s	22.879us	5	5	100.00
		spi_host_same_csr_outstanding	7.000s	62.070us	20	20	100.00
V2		TOTAL			688	690	99.71
V2S	tl_intg_err	spi_host_tl_intg_err	7.000s	79.578us	20	20	100.00
		spi_host_sec_cm	3.000s	407.985us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	7.000s	79.578us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_host_upper_range_clkdiv	53.817m	100.010ms	3	10	30.00
		TOTAL			831	840	98.93

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	15	15	14	93.33
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
91.01	90.92	83.18	92.77	89.84	95.70	100.00	95.07	90.87

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 4 failures:
- Test spi_host_upper_range_clkdiv has 4 failures.
  - 0.spi_host_upper_range_clkdiv.45075841653220695752881584036620764490779356135163600563979756674841311406012
    Line 293, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 100012116099 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xdd7c5e94, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
  UVM_INFO @ 100012116099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.spi_host_upper_range_clkdiv.97183271150447427985798196780920909844305136214040969584113564452801149137032
    Line 342, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 100009848011 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xdf05f5d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
  UVM_INFO @ 100009848011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
Job spi_host-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
- Test spi_host_upper_range_clkdiv has 3 failures.
  - 1.spi_host_upper_range_clkdiv.67019032729857940907996231901564490476845894075612495188821020662252491666443
    Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
```
  Job ID: smart:11fff822-b1b1-4c9a-8c5e-3c2b28ed139a
```
  - 8.spi_host_upper_range_clkdiv.101684605588528473933729626567862825784769623990212373799115210473336772687435
    Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_upper_range_clkdiv/latest/run.log
```
  Job ID: smart:c2a8cdea-555c-4e20-bf27-ad22280f80ec
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=89) has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 8.spi_host_status_stall.18033903463294737411992968569353450156600144499332975265313412795033467431903
    Line 936, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 10356456043 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa430d794, Comparison=CompareOpEq, exp_data=0x1, call_count=89)
  UVM_INFO @ 10356456043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=81) has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 11.spi_host_status_stall.34273179802308767812889987810462060637420983581659618396530130295552113663155
    Line 876, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 11182043282 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xd203de14, Comparison=CompareOpEq, exp_data=0x1, call_count=81)
  UVM_INFO @ 11182043282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `76588857da`