SPI_HOST Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: `f1535c5540`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	11.750m	29.613ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	12.000s	18.961us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	18.286us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	58.455us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	24.516us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	8.000s	22.966us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	18.286us	20	20	100.00
		spi_host_csr_aliasing	3.000s	24.516us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	13.000s	26.492us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	64.517us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	4.000s	406.505us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	1.850m	2.440ms	50	50	100.00
		spi_host_error_cmd	8.000s	17.712us	50	50	100.00
		spi_host_event	13.950m	19.892ms	50	50	100.00
V2	clock_rate	spi_host_speed	30.000s	602.412us	50	50	100.00
V2	speed	spi_host_speed	30.000s	602.412us	50	50	100.00
V2	chip_select_timing	spi_host_speed	30.000s	602.412us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	1.483m	5.205ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	228.131us	50	50	100.00
V2	cpol_cpha	spi_host_speed	30.000s	602.412us	50	50	100.00
V2	full_cycle	spi_host_speed	30.000s	602.412us	50	50	100.00
V2	duplex	spi_host_smoke	11.750m	29.613ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	11.750m	29.613ms	50	50	100.00
V2	stress_all	spi_host_stress_all	1.767m	2.288ms	50	50	100.00
V2	spien	spi_host_spien	5.250m	45.889ms	50	50	100.00
V2	stall	spi_host_status_stall	8.083m	12.132ms	49	50	98.00
V2	Idlecsbactive	spi_host_idlecsbactive	16.000s	4.976ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	1.850m	2.440ms	50	50	100.00
V2	alert_test	spi_host_alert_test	3.000s	134.647us	50	50	100.00
V2	intr_test	spi_host_intr_test	7.000s	48.502us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	14.000s	369.103us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	14.000s	369.103us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	12.000s	18.961us	5	5	100.00
		spi_host_csr_rw	3.000s	18.286us	20	20	100.00
		spi_host_csr_aliasing	3.000s	24.516us	5	5	100.00
		spi_host_same_csr_outstanding	8.000s	59.671us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	12.000s	18.961us	5	5	100.00
		spi_host_csr_rw	3.000s	18.286us	20	20	100.00
		spi_host_csr_aliasing	3.000s	24.516us	5	5	100.00
		spi_host_same_csr_outstanding	8.000s	59.671us	20	20	100.00
V2		TOTAL			689	690	99.86
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	381.657us	20	20	100.00
		spi_host_sec_cm	3.000s	65.861us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	381.657us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_host_upper_range_clkdiv	59.617m	167.372ms	3	10	30.00
		TOTAL			832	840	99.05

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	15	15	14	93.33
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
91.02	90.92	83.18	92.77	89.92	95.70	100.00	95.07	90.87

Failure Buckets

Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 2 failures:
- Test spi_host_upper_range_clkdiv has 2 failures.
  - 0.spi_host_upper_range_clkdiv.37059617966422496682279985647842183326556467307509551764858356733138381124025
    Line 323, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 100008580389 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xdfdb1094, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
  UVM_INFO @ 100008580389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.spi_host_upper_range_clkdiv.46670222455661356726494684054573072581326098622014779421409147109711359483080
    Line 323, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 100005210903 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe1aa9394, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
  UVM_INFO @ 100005210903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 1 failures:
- Test spi_host_upper_range_clkdiv has 1 failures.
  - 1.spi_host_upper_range_clkdiv.91620086053936185184105144913953292905301035157998844695410215004667073440553
    Line 331, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 100022178051 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xd180d754, Comparison=CompareOpEq, exp_data=0x0, call_count=14)
  UVM_INFO @ 100022178051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 1 failures:
- Test spi_host_upper_range_clkdiv has 1 failures.
  - 3.spi_host_upper_range_clkdiv.100053718806573058812324850192835279154219340936427697128704788394924006461257
    Line 330, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 100002809252 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xa70d4694, Comparison=CompareOpEq, exp_data=0x0, call_count=14)
  UVM_INFO @ 100002809252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:
- Test spi_host_upper_range_clkdiv has 1 failures.
  - 4.spi_host_upper_range_clkdiv.87113062224442310655447961205413199746754093365705576199405632633670819389798
    Line 303, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 100003788170 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xffa1e114, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
  UVM_INFO @ 100003788170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job spi_host-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test spi_host_upper_range_clkdiv has 1 failures.
  - 7.spi_host_upper_range_clkdiv.17162239078178658358184991767382658537214439821935785781348959935457979127694
    Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_upper_range_clkdiv/latest/run.log
```
  Job ID: smart:3843f65f-9b29-4a83-be60-1130b38ab69c
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
- Test spi_host_upper_range_clkdiv has 1 failures.
  - 8.spi_host_upper_range_clkdiv.27993693129709286168764849312315647238962871048826470619843820022105980827231
    Line 351, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 167372015566 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x9c4d9054, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
  UVM_INFO @ 167372015566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=91) has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 10.spi_host_status_stall.81905684184237342274745364642578731895633194808603122100458823248108215134523
    Line 941, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 10303332558 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x1a8b8914, Comparison=CompareOpEq, exp_data=0x1, call_count=91)
  UVM_INFO @ 10303332558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SPI_HOST Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: f1535c5540

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `f1535c5540`