SPI_HOST Simulation Results

Monday August 19 2024 23:02:17 UTC

GitHub Revision: e45ccd274a

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 28901767565311589526059483176077826609560752276120463932311122284088110669824

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 11.883m 71.906ms 50 50 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 4.000s 17.702us 5 5 100.00
V1 csr_rw spi_host_csr_rw 3.000s 25.115us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 162.009us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 2.000s 46.915us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 3.000s 127.509us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 3.000s 25.115us 20 20 100.00
spi_host_csr_aliasing 2.000s 46.915us 5 5 100.00
V1 mem_walk spi_host_mem_walk 4.000s 45.412us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 83.640us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 performance spi_host_performance 4.000s 95.119us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.567m 12.868ms 50 50 100.00
spi_host_error_cmd 3.000s 19.979us 50 50 100.00
spi_host_event 11.567m 16.927ms 50 50 100.00
V2 clock_rate spi_host_speed 31.000s 605.686us 50 50 100.00
V2 speed spi_host_speed 31.000s 605.686us 50 50 100.00
V2 chip_select_timing spi_host_speed 31.000s 605.686us 50 50 100.00
V2 sw_reset spi_host_sw_reset 2.900m 11.540ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 3.000s 408.059us 50 50 100.00
V2 cpol_cpha spi_host_speed 31.000s 605.686us 50 50 100.00
V2 full_cycle spi_host_speed 31.000s 605.686us 50 50 100.00
V2 duplex spi_host_smoke 11.883m 71.906ms 50 50 100.00
V2 tx_rx_only spi_host_smoke 11.883m 71.906ms 50 50 100.00
V2 stress_all spi_host_stress_all 1.950m 7.721ms 50 50 100.00
V2 spien spi_host_spien 4.983m 6.442ms 49 50 98.00
V2 stall spi_host_status_stall 8.283m 25.270ms 46 50 92.00
V2 Idlecsbactive spi_host_idlecsbactive 37.000s 2.726ms 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 2.567m 12.868ms 50 50 100.00
V2 alert_test spi_host_alert_test 3.000s 16.929us 50 50 100.00
V2 intr_test spi_host_intr_test 3.000s 42.947us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 6.000s 168.186us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 6.000s 168.186us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 4.000s 17.702us 5 5 100.00
spi_host_csr_rw 3.000s 25.115us 20 20 100.00
spi_host_csr_aliasing 2.000s 46.915us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 81.090us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 4.000s 17.702us 5 5 100.00
spi_host_csr_rw 3.000s 25.115us 20 20 100.00
spi_host_csr_aliasing 2.000s 46.915us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 81.090us 20 20 100.00
V2 TOTAL 685 690 99.28
V2S tl_intg_err spi_host_tl_intg_err 4.000s 246.576us 20 20 100.00
spi_host_sec_cm 3.000s 534.990us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 4.000s 246.576us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 50.950m 100.003ms 0 10 0.00
TOTAL 825 840 98.21

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 8 100.00
V2 15 15 13 86.67
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.01 90.92 83.18 92.77 89.77 95.70 100.00 95.07 90.87

Failure Buckets

Past Results