SPI_HOST Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: 34b8fc33e3

Branch: earlgrey_1_0_0_2024_08_20_RC0

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 7.133m 16.534ms 50 50 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 3.000s 19.478us 5 5 100.00
V1 csr_rw spi_host_csr_rw 10.000s 26.720us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 6.000s 637.081us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 4.000s 45.478us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 26.000s 23.511us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 10.000s 26.720us 20 20 100.00
spi_host_csr_aliasing 4.000s 45.478us 5 5 100.00
V1 mem_walk spi_host_mem_walk 3.000s 17.069us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 4.000s 42.920us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 performance spi_host_performance 48.000s 31.764us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 3.550m 12.514ms 50 50 100.00
spi_host_error_cmd 48.000s 16.236us 50 50 100.00
spi_host_event 17.900m 303.489ms 50 50 100.00
V2 clock_rate spi_host_speed 43.000s 100.877us 50 50 100.00
V2 speed spi_host_speed 43.000s 100.877us 50 50 100.00
V2 chip_select_timing spi_host_speed 43.000s 100.877us 50 50 100.00
V2 sw_reset spi_host_sw_reset 6.150m 20.594ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 39.000s 553.580us 50 50 100.00
V2 cpol_cpha spi_host_speed 43.000s 100.877us 50 50 100.00
V2 full_cycle spi_host_speed 43.000s 100.877us 50 50 100.00
V2 duplex spi_host_smoke 7.133m 16.534ms 50 50 100.00
V2 tx_rx_only spi_host_smoke 7.133m 16.534ms 50 50 100.00
V2 stress_all spi_host_stress_all 8.450m 22.589ms 49 50 98.00
V2 spien spi_host_spien 7.517m 11.189ms 50 50 100.00
V2 stall spi_host_status_stall 7.917m 10.619ms 46 50 92.00
V2 Idlecsbactive spi_host_idlecsbactive 56.000s 2.109ms 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 3.550m 12.514ms 50 50 100.00
V2 alert_test spi_host_alert_test 42.000s 23.989us 50 50 100.00
V2 intr_test spi_host_intr_test 40.000s 23.705us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 11.000s 31.410us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 11.000s 31.410us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 3.000s 19.478us 5 5 100.00
spi_host_csr_rw 10.000s 26.720us 20 20 100.00
spi_host_csr_aliasing 4.000s 45.478us 5 5 100.00
spi_host_same_csr_outstanding 11.000s 20.333us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 3.000s 19.478us 5 5 100.00
spi_host_csr_rw 10.000s 26.720us 20 20 100.00
spi_host_csr_aliasing 4.000s 45.478us 5 5 100.00
spi_host_same_csr_outstanding 11.000s 20.333us 20 20 100.00
V2 TOTAL 685 690 99.28
V2S tl_intg_err spi_host_tl_intg_err 10.000s 159.320us 20 20 100.00
spi_host_sec_cm 4.000s 62.619us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 10.000s 159.320us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 52.050m 100.004ms 5 10 50.00
TOTAL 830 840 98.81

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 8 100.00
V2 15 15 13 86.67
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.01 90.92 83.18 92.77 89.84 95.70 100.00 95.07 90.87

Failure Buckets

Past Results