SPI_HOST Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: 0825c81be0

Branch: os_regression_2024_08_22

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 8.150m 48.621ms 50 50 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 3.000s 30.425us 5 5 100.00
V1 csr_rw spi_host_csr_rw 3.000s 23.183us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 365.943us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 83.715us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 4.000s 28.090us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 3.000s 23.183us 20 20 100.00
spi_host_csr_aliasing 3.000s 83.715us 5 5 100.00
V1 mem_walk spi_host_mem_walk 3.000s 17.010us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 37.673us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 performance spi_host_performance 4.000s 122.737us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 1.617m 8.356ms 50 50 100.00
spi_host_error_cmd 3.000s 15.801us 50 50 100.00
spi_host_event 16.750m 295.355ms 50 50 100.00
V2 clock_rate spi_host_speed 22.000s 470.958us 50 50 100.00
V2 speed spi_host_speed 22.000s 470.958us 50 50 100.00
V2 chip_select_timing spi_host_speed 22.000s 470.958us 50 50 100.00
V2 sw_reset spi_host_sw_reset 3.100m 10.024ms 49 50 98.00
V2 passthrough_mode spi_host_passthrough_mode 4.000s 201.284us 50 50 100.00
V2 cpol_cpha spi_host_speed 22.000s 470.958us 50 50 100.00
V2 full_cycle spi_host_speed 22.000s 470.958us 50 50 100.00
V2 duplex spi_host_smoke 8.150m 48.621ms 50 50 100.00
V2 tx_rx_only spi_host_smoke 8.150m 48.621ms 50 50 100.00
V2 stress_all spi_host_stress_all 3.950m 15.329ms 49 50 98.00
V2 spien spi_host_spien 3.583m 5.357ms 50 50 100.00
V2 stall spi_host_status_stall 7.600m 12.699ms 48 50 96.00
V2 Idlecsbactive spi_host_idlecsbactive 45.000s 1.857ms 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 1.617m 8.356ms 50 50 100.00
V2 alert_test spi_host_alert_test 4.000s 44.173us 50 50 100.00
V2 intr_test spi_host_intr_test 3.000s 54.117us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 5.000s 2.133ms 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 5.000s 2.133ms 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 3.000s 30.425us 5 5 100.00
spi_host_csr_rw 3.000s 23.183us 20 20 100.00
spi_host_csr_aliasing 3.000s 83.715us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 29.683us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 3.000s 30.425us 5 5 100.00
spi_host_csr_rw 3.000s 23.183us 20 20 100.00
spi_host_csr_aliasing 3.000s 83.715us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 29.683us 20 20 100.00
V2 TOTAL 686 690 99.42
V2S tl_intg_err spi_host_tl_intg_err 4.000s 349.875us 20 20 100.00
spi_host_sec_cm 3.000s 68.424us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 4.000s 349.875us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 55.917m 100.003ms 4 10 40.00
TOTAL 830 840 98.81

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 8 100.00
V2 15 15 12 80.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.02 90.92 83.18 92.77 89.92 95.70 100.00 95.07 90.87

Failure Buckets

Past Results