SPI_HOST Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: 78ad89d1aa

Branch: os_regression_2024_09_23

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 6.433m 8.457ms 50 50 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 4.000s 29.520us 5 5 100.00
V1 csr_rw spi_host_csr_rw 55.000s 17.994us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 6.000s 148.656us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 56.555us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 1.400m 309.132us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 55.000s 17.994us 20 20 100.00
spi_host_csr_aliasing 3.000s 56.555us 5 5 100.00
V1 mem_walk spi_host_mem_walk 4.000s 14.446us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 4.000s 21.443us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 performance spi_host_performance 21.000s 112.378us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 3.350m 40.549ms 50 50 100.00
spi_host_error_cmd 17.000s 19.973us 50 50 100.00
spi_host_event 13.317m 21.509ms 50 50 100.00
V2 clock_rate spi_host_speed 51.000s 3.891ms 50 50 100.00
V2 speed spi_host_speed 51.000s 3.891ms 50 50 100.00
V2 chip_select_timing spi_host_speed 51.000s 3.891ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 1.550m 2.843ms 48 50 96.00
V2 passthrough_mode spi_host_passthrough_mode 25.000s 171.307us 50 50 100.00
V2 cpol_cpha spi_host_speed 51.000s 3.891ms 50 50 100.00
V2 full_cycle spi_host_speed 51.000s 3.891ms 50 50 100.00
V2 duplex spi_host_smoke 6.433m 8.457ms 50 50 100.00
V2 tx_rx_only spi_host_smoke 6.433m 8.457ms 50 50 100.00
V2 stress_all spi_host_stress_all 6.917m 22.507ms 49 50 98.00
V2 spien spi_host_spien 5.167m 6.769ms 50 50 100.00
V2 stall spi_host_status_stall 6.233m 9.027ms 48 50 96.00
V2 Idlecsbactive spi_host_idlecsbactive 57.000s 3.548ms 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 3.350m 40.549ms 50 50 100.00
V2 alert_test spi_host_alert_test 17.000s 18.554us 50 50 100.00
V2 intr_test spi_host_intr_test 1.400m 36.139us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 1.550m 96.714us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 1.550m 96.714us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 4.000s 29.520us 5 5 100.00
spi_host_csr_rw 55.000s 17.994us 20 20 100.00
spi_host_csr_aliasing 3.000s 56.555us 5 5 100.00
spi_host_same_csr_outstanding 1.400m 18.576us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 4.000s 29.520us 5 5 100.00
spi_host_csr_rw 55.000s 17.994us 20 20 100.00
spi_host_csr_aliasing 3.000s 56.555us 5 5 100.00
spi_host_same_csr_outstanding 1.400m 18.576us 20 20 100.00
V2 TOTAL 685 690 99.28
V2S tl_intg_err spi_host_tl_intg_err 46.000s 414.244us 20 20 100.00
spi_host_sec_cm 4.000s 42.809us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 46.000s 414.244us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 58.200m 100.004ms 5 10 50.00
TOTAL 830 840 98.81

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 8 100.00
V2 15 15 12 80.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.03 90.92 83.18 92.77 89.84 95.70 100.00 95.22 90.87

Failure Buckets

Past Results