SPI_HOST Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: 1cb1c3d135

Branch: os_regression_2024_10_02

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 8.617m 37.864ms 50 50 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 4.000s 28.889us 5 5 100.00
V1 csr_rw spi_host_csr_rw 54.000s 26.182us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 7.000s 211.330us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 4.000s 56.859us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 57.000s 23.901us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 54.000s 26.182us 20 20 100.00
spi_host_csr_aliasing 4.000s 56.859us 5 5 100.00
V1 mem_walk spi_host_mem_walk 4.000s 25.915us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 4.000s 21.282us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 performance spi_host_performance 24.000s 34.658us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.883m 14.093ms 50 50 100.00
spi_host_error_cmd 21.000s 29.294us 50 50 100.00
spi_host_event 18.650m 27.822ms 50 50 100.00
V2 clock_rate spi_host_speed 38.000s 402.377us 50 50 100.00
V2 speed spi_host_speed 38.000s 402.377us 50 50 100.00
V2 chip_select_timing spi_host_speed 38.000s 402.377us 50 50 100.00
V2 sw_reset spi_host_sw_reset 4.833m 10.141ms 49 50 98.00
V2 passthrough_mode spi_host_passthrough_mode 17.000s 321.954us 50 50 100.00
V2 cpol_cpha spi_host_speed 38.000s 402.377us 50 50 100.00
V2 full_cycle spi_host_speed 38.000s 402.377us 50 50 100.00
V2 duplex spi_host_smoke 8.617m 37.864ms 50 50 100.00
V2 tx_rx_only spi_host_smoke 8.617m 37.864ms 50 50 100.00
V2 stress_all spi_host_stress_all 4.250m 15.270ms 49 50 98.00
V2 spien spi_host_spien 5.250m 14.510ms 50 50 100.00
V2 stall spi_host_status_stall 6.933m 9.169ms 45 50 90.00
V2 Idlecsbactive spi_host_idlecsbactive 40.000s 8.146ms 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 2.883m 14.093ms 50 50 100.00
V2 alert_test spi_host_alert_test 25.000s 15.969us 50 50 100.00
V2 intr_test spi_host_intr_test 1.000m 47.037us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 58.000s 151.328us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 58.000s 151.328us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 4.000s 28.889us 5 5 100.00
spi_host_csr_rw 54.000s 26.182us 20 20 100.00
spi_host_csr_aliasing 4.000s 56.859us 5 5 100.00
spi_host_same_csr_outstanding 43.000s 95.191us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 4.000s 28.889us 5 5 100.00
spi_host_csr_rw 54.000s 26.182us 20 20 100.00
spi_host_csr_aliasing 4.000s 56.859us 5 5 100.00
spi_host_same_csr_outstanding 43.000s 95.191us 20 20 100.00
V2 TOTAL 683 690 98.99
V2S tl_intg_err spi_host_tl_intg_err 1.000m 45.970us 20 20 100.00
spi_host_sec_cm 3.000s 55.491us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 1.000m 45.970us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 49.083m 100.001ms 3 10 30.00
TOTAL 826 840 98.33

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 8 100.00
V2 15 15 12 80.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.00 90.89 83.13 92.75 89.76 95.70 100.00 95.22 90.87

Failure Buckets

Past Results