SPI_HOST Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: 25b1acbf68

Branch: os_regression_2024_09_10

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 11.733m 52.596ms 50 50 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 1.550m 16.386us 5 5 100.00
V1 csr_rw spi_host_csr_rw 1.200m 28.043us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 31.000s 156.322us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 43.000s 32.621us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 1.100m 72.346us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 1.200m 28.043us 20 20 100.00
spi_host_csr_aliasing 43.000s 32.621us 5 5 100.00
V1 mem_walk spi_host_mem_walk 1.550m 105.472us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 1.583m 20.595us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 performance spi_host_performance 59.000s 100.050us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 3.417m 14.936ms 50 50 100.00
spi_host_error_cmd 59.000s 42.084us 50 50 100.00
spi_host_event 8.983m 26.098ms 50 50 100.00
V2 clock_rate spi_host_speed 1.100m 84.575us 50 50 100.00
V2 speed spi_host_speed 1.100m 84.575us 50 50 100.00
V2 chip_select_timing spi_host_speed 1.100m 84.575us 50 50 100.00
V2 sw_reset spi_host_sw_reset 5.783m 29.878ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 57.000s 203.690us 50 50 100.00
V2 cpol_cpha spi_host_speed 1.100m 84.575us 50 50 100.00
V2 full_cycle spi_host_speed 1.100m 84.575us 50 50 100.00
V2 duplex spi_host_smoke 11.733m 52.596ms 50 50 100.00
V2 tx_rx_only spi_host_smoke 11.733m 52.596ms 50 50 100.00
V2 stress_all spi_host_stress_all 1.833m 4.182ms 50 50 100.00
V2 spien spi_host_spien 2.733m 38.376ms 50 50 100.00
V2 stall spi_host_status_stall 7.133m 10.157ms 49 50 98.00
V2 Idlecsbactive spi_host_idlecsbactive 58.000s 128.139us 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 3.417m 14.936ms 50 50 100.00
V2 alert_test spi_host_alert_test 59.000s 16.696us 50 50 100.00
V2 intr_test spi_host_intr_test 1.567m 27.935us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 1.117m 211.449us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 1.117m 211.449us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 1.550m 16.386us 5 5 100.00
spi_host_csr_rw 1.200m 28.043us 20 20 100.00
spi_host_csr_aliasing 43.000s 32.621us 5 5 100.00
spi_host_same_csr_outstanding 1.100m 20.239us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 1.550m 16.386us 5 5 100.00
spi_host_csr_rw 1.200m 28.043us 20 20 100.00
spi_host_csr_aliasing 43.000s 32.621us 5 5 100.00
spi_host_same_csr_outstanding 1.100m 20.239us 20 20 100.00
V2 TOTAL 689 690 99.86
V2S tl_intg_err spi_host_tl_intg_err 1.550m 101.378us 20 20 100.00
spi_host_sec_cm 30.000s 174.009us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 1.550m 101.378us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 58.550m 100.003ms 3 10 30.00
TOTAL 832 840 99.05

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 8 100.00
V2 15 15 14 93.33
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.02 90.92 83.18 92.77 89.92 95.70 100.00 95.07 90.87

Failure Buckets

Past Results