SPI_HOST Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: 8a1401d614

Branch: os_regression_2024_10_11

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 10.933m 67.273ms 49 50 98.00
V1 csr_hw_reset spi_host_csr_hw_reset 1.183m 37.208us 5 5 100.00
V1 csr_rw spi_host_csr_rw 1.817m 16.077us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 1.383m 123.914us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 1.683m 25.470us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 1.717m 19.538us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 1.817m 16.077us 20 20 100.00
spi_host_csr_aliasing 1.683m 25.470us 5 5 100.00
V1 mem_walk spi_host_mem_walk 1.183m 15.123us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 1.183m 21.894us 5 5 100.00
V1 TOTAL 114 115 99.13
V2 performance spi_host_performance 21.000s 31.132us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 1.633m 43.622ms 50 50 100.00
spi_host_error_cmd 23.000s 55.778us 50 50 100.00
spi_host_event 13.483m 41.064ms 50 50 100.00
V2 clock_rate spi_host_speed 28.000s 1.950ms 50 50 100.00
V2 speed spi_host_speed 28.000s 1.950ms 50 50 100.00
V2 chip_select_timing spi_host_speed 28.000s 1.950ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 3.717m 6.877ms 49 50 98.00
V2 passthrough_mode spi_host_passthrough_mode 24.000s 634.688us 50 50 100.00
V2 cpol_cpha spi_host_speed 28.000s 1.950ms 50 50 100.00
V2 full_cycle spi_host_speed 28.000s 1.950ms 50 50 100.00
V2 duplex spi_host_smoke 10.933m 67.273ms 49 50 98.00
V2 tx_rx_only spi_host_smoke 10.933m 67.273ms 49 50 98.00
V2 stress_all spi_host_stress_all 2.400m 9.482ms 50 50 100.00
V2 spien spi_host_spien 7.983m 17.228ms 50 50 100.00
V2 stall spi_host_status_stall 9.133m 11.023ms 48 50 96.00
V2 Idlecsbactive spi_host_idlecsbactive 1.133m 6.794ms 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 1.633m 43.622ms 50 50 100.00
V2 alert_test spi_host_alert_test 28.000s 18.479us 50 50 100.00
V2 intr_test spi_host_intr_test 1.717m 61.056us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 1.817m 125.094us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 1.817m 125.094us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 1.183m 37.208us 5 5 100.00
spi_host_csr_rw 1.817m 16.077us 20 20 100.00
spi_host_csr_aliasing 1.683m 25.470us 5 5 100.00
spi_host_same_csr_outstanding 1.083m 87.926us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 1.183m 37.208us 5 5 100.00
spi_host_csr_rw 1.817m 16.077us 20 20 100.00
spi_host_csr_aliasing 1.683m 25.470us 5 5 100.00
spi_host_same_csr_outstanding 1.083m 87.926us 20 20 100.00
V2 TOTAL 687 690 99.57
V2S tl_intg_err spi_host_tl_intg_err 1.650m 892.183us 20 20 100.00
spi_host_sec_cm 4.000s 320.573us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 1.650m 892.183us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 44.117m 100.003ms 0 10 0.00
TOTAL 826 840 98.33

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 7 87.50
V2 15 15 13 86.67
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.00 90.89 83.13 92.75 89.76 95.70 100.00 95.22 90.87

Failure Buckets

Past Results