SPI_HOST Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: 29d22a60a2

Branch: os_regression_2024_10_08

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 9.533m 25.263ms 50 50 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 3.000s 36.779us 5 5 100.00
V1 csr_rw spi_host_csr_rw 1.333m 20.002us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 6.000s 207.865us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 4.000s 37.804us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 1.383m 26.283us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 1.333m 20.002us 20 20 100.00
spi_host_csr_aliasing 4.000s 37.804us 5 5 100.00
V1 mem_walk spi_host_mem_walk 3.000s 17.924us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 4.000s 20.341us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 performance spi_host_performance 1.350m 29.110us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.833m 3.457ms 50 50 100.00
spi_host_error_cmd 1.333m 20.706us 50 50 100.00
spi_host_event 17.783m 145.523ms 50 50 100.00
V2 clock_rate spi_host_speed 1.617m 1.121ms 50 50 100.00
V2 speed spi_host_speed 1.617m 1.121ms 50 50 100.00
V2 chip_select_timing spi_host_speed 1.617m 1.121ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 2.900m 7.401ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 1.383m 249.524us 50 50 100.00
V2 cpol_cpha spi_host_speed 1.617m 1.121ms 50 50 100.00
V2 full_cycle spi_host_speed 1.617m 1.121ms 50 50 100.00
V2 duplex spi_host_smoke 9.533m 25.263ms 50 50 100.00
V2 tx_rx_only spi_host_smoke 9.533m 25.263ms 50 50 100.00
V2 stress_all spi_host_stress_all 10.600m 24.469ms 49 50 98.00
V2 spien spi_host_spien 6.150m 6.958ms 49 50 98.00
V2 stall spi_host_status_stall 8.783m 10.196ms 44 50 88.00
V2 Idlecsbactive spi_host_idlecsbactive 1.367m 821.365us 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 2.833m 3.457ms 50 50 100.00
V2 alert_test spi_host_alert_test 1.433m 18.313us 50 50 100.00
V2 intr_test spi_host_intr_test 1.467m 50.042us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 1.317m 85.675us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 1.317m 85.675us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 3.000s 36.779us 5 5 100.00
spi_host_csr_rw 1.333m 20.002us 20 20 100.00
spi_host_csr_aliasing 4.000s 37.804us 5 5 100.00
spi_host_same_csr_outstanding 1.400m 66.217us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 3.000s 36.779us 5 5 100.00
spi_host_csr_rw 1.333m 20.002us 20 20 100.00
spi_host_csr_aliasing 4.000s 37.804us 5 5 100.00
spi_host_same_csr_outstanding 1.400m 66.217us 20 20 100.00
V2 TOTAL 682 690 98.84
V2S tl_intg_err spi_host_tl_intg_err 1.617m 414.871us 20 20 100.00
spi_host_sec_cm 4.000s 65.151us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 1.617m 414.871us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 52.183m 100.005ms 2 10 20.00
TOTAL 824 840 98.10

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 8 100.00
V2 15 15 12 80.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
90.98 90.89 83.13 92.75 89.60 95.70 100.00 95.22 90.87

Failure Buckets

Past Results