SPI_HOST Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: 7e34e67ade

Branch: os_regression_2024_09_17

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 10.450m 23.780ms 50 50 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 41.000s 19.008us 5 5 100.00
V1 csr_rw spi_host_csr_rw 1.933m 46.318us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 35.000s 1.007ms 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 32.000s 18.650us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 1.817m 26.759us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 1.933m 46.318us 20 20 100.00
spi_host_csr_aliasing 32.000s 18.650us 5 5 100.00
V1 mem_walk spi_host_mem_walk 41.000s 27.944us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 41.000s 24.584us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 performance spi_host_performance 1.133m 466.573us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.000m 36.451ms 50 50 100.00
spi_host_error_cmd 1.550m 46.959us 50 50 100.00
spi_host_event 19.517m 423.068ms 50 50 100.00
V2 clock_rate spi_host_speed 1.600m 51.614us 50 50 100.00
V2 speed spi_host_speed 1.600m 51.614us 50 50 100.00
V2 chip_select_timing spi_host_speed 1.600m 51.614us 50 50 100.00
V2 sw_reset spi_host_sw_reset 2.883m 5.825ms 49 50 98.00
V2 passthrough_mode spi_host_passthrough_mode 49.000s 111.595us 50 50 100.00
V2 cpol_cpha spi_host_speed 1.600m 51.614us 50 50 100.00
V2 full_cycle spi_host_speed 1.600m 51.614us 50 50 100.00
V2 duplex spi_host_smoke 10.450m 23.780ms 50 50 100.00
V2 tx_rx_only spi_host_smoke 10.450m 23.780ms 50 50 100.00
V2 stress_all spi_host_stress_all 2.733m 10.039ms 50 50 100.00
V2 spien spi_host_spien 6.683m 28.002ms 49 50 98.00
V2 stall spi_host_status_stall 17.833m 20.690ms 47 50 94.00
V2 Idlecsbactive spi_host_idlecsbactive 1.633m 26.800us 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 2.000m 36.451ms 50 50 100.00
V2 alert_test spi_host_alert_test 1.633m 72.345us 50 50 100.00
V2 intr_test spi_host_intr_test 2.117m 15.214us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 2.367m 53.240us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 2.367m 53.240us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 41.000s 19.008us 5 5 100.00
spi_host_csr_rw 1.933m 46.318us 20 20 100.00
spi_host_csr_aliasing 32.000s 18.650us 5 5 100.00
spi_host_same_csr_outstanding 1.950m 15.762us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 41.000s 19.008us 5 5 100.00
spi_host_csr_rw 1.933m 46.318us 20 20 100.00
spi_host_csr_aliasing 32.000s 18.650us 5 5 100.00
spi_host_same_csr_outstanding 1.950m 15.762us 20 20 100.00
V2 TOTAL 685 690 99.28
V2S tl_intg_err spi_host_tl_intg_err 1.983m 140.462us 20 20 100.00
spi_host_sec_cm 1.983m 153.889us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 1.983m 140.462us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 59.167m 100.003ms 0 10 0.00
TOTAL 825 840 98.21

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 8 100.00
V2 15 15 12 80.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.02 90.92 83.18 92.77 89.84 95.70 100.00 95.22 90.46

Failure Buckets

Past Results