SRAM_CTRL/MAIN Simulation Results

Thursday March 14 2024 19:02:18 UTC

GitHub Revision: e844018f2c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 83239673812975098462159483702727474484560953854893181354811398969250076096082

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.915m 11.492ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.670s 19.108us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.670s 27.317us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.190s 837.161us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.680s 23.761us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 5.470s 1.536ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.670s 27.317us 20 20 100.00
sram_ctrl_csr_aliasing 0.680s 23.761us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 5.974m 275.207ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 2.696m 30.082ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 42.663m 106.887ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.154m 100.981ms 50 50 100.00
V2 bijection sram_ctrl_bijection 46.418m 155.716ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 29.895m 76.896ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 1.791m 67.748ms 50 50 100.00
V2 executable sram_ctrl_executable 29.630m 24.136ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.477m 879.121us 50 50 100.00
sram_ctrl_partial_access_b2b 9.528m 48.468ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.768m 1.600ms 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.485m 3.115ms 50 50 100.00
V2 regwen sram_ctrl_regwen 30.081m 86.979ms 49 50 98.00
V2 ram_cfg sram_ctrl_ram_cfg 4.760s 4.772ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.226h 328.895ms 48 50 96.00
V2 alert_test sram_ctrl_alert_test 0.700s 35.249us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.570s 514.617us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.570s 514.617us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.670s 19.108us 5 5 100.00
sram_ctrl_csr_rw 0.670s 27.317us 20 20 100.00
sram_ctrl_csr_aliasing 0.680s 23.761us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.770s 318.502us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.670s 19.108us 5 5 100.00
sram_ctrl_csr_rw 0.670s 27.317us 20 20 100.00
sram_ctrl_csr_aliasing 0.680s 23.761us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.770s 318.502us 20 20 100.00
V2 TOTAL 737 740 99.59
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 59.330s 32.100ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.630s 1.988ms 5 5 100.00
sram_ctrl_tl_intg_err 2.480s 671.608us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.630s 1.988ms 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.480s 671.608us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 30.081m 86.979ms 49 50 98.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.670s 27.317us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 29.630m 24.136ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 29.630m 24.136ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 29.630m 24.136ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 1.791m 67.748ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 59.330s 32.100ms 20 20 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.915m 11.492ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.915m 11.492ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 29.630m 24.136ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.630s 1.988ms 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 1.791m 67.748ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.630s 1.988ms 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.630s 1.988ms 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.915m 11.492ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.630s 1.988ms 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 5.008m 34.804ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1037 1040 99.71

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 14 87.50
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.41 100.00 97.91 100.00 100.00 99.72 99.70 98.52

Failure Buckets

Past Results