SRAM_CTRL/MAIN Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: c187a82ee8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.830m	781.009us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.710s	15.806us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.730s	149.260us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.110s	120.565us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.730s	63.863us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.510s	369.498us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.730s	149.260us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	63.863us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.134m	198.689ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.841m	18.081ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	23.717m	68.125ms	48	50	96.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	8.122m	26.675ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	45.059m	188.610ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	33.803m	21.671ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.697m	15.801ms	50	50	100.00
V2	executable	sram_ctrl_executable	32.205m	67.952ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	3.116m	1.322ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.561m	45.140ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.564m	768.138us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	3.015m	985.140us	50	50	100.00
V2	regwen	sram_ctrl_regwen	32.015m	67.540ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.460s	6.732ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.566h	938.020ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	0.720s	37.078us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.650s	160.788us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.650s	160.788us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.710s	15.806us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	149.260us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	63.863us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.890s	25.429us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.710s	15.806us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	149.260us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	63.863us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.890s	25.429us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	57.480s	24.281ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.290s	333.752us	5	5	100.00
		sram_ctrl_tl_intg_err	2.640s	261.646us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.290s	333.752us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.640s	261.646us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	32.015m	67.540ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.730s	149.260us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	32.205m	67.952ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	32.205m	67.952ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	32.205m	67.952ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.697m	15.801ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	57.480s	24.281ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.830m	781.009us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.830m	781.009us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	32.205m	67.952ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.290s	333.752us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.697m	15.801ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.290s	333.752us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.290s	333.752us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.830m	781.009us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.290s	333.752us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	9.039m	62.096ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1035	1040	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.41	100.00	97.91	100.00	100.00	99.72	99.70	98.52

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 2 failures:

  • Test sram_ctrl_multiple_keys has 2 failures.

    • 1.sram_ctrl_multiple_keys.41643468163102228517821628714148434840749038912412694659432393701590441259700
      Line 282, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_multiple_keys/latest/run.log

        UVM_FATAL @ 48382944503 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x52298b53
        UVM_INFO @ 48382944503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 25.sram_ctrl_multiple_keys.35526763158842088661781078964336730295239872993825824620252060127624597290312
      Line 290, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/25.sram_ctrl_multiple_keys/latest/run.log

        UVM_FATAL @ 116381447109 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xdf375f74
        UVM_INFO @ 116381447109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test sram_ctrl_bijection has 1 failures.

    • 11.sram_ctrl_bijection.20618625853224736509266366658099012661909013823276736867430561515285140521138
      Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_bijection/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:827) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 1 failures.

    • 37.sram_ctrl_stress_all_with_rand_reset.79684974469719198494411191251728232033309524854732785563929594582874046217280
      Line 321, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/37.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8470056005 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 8470056005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_executable has 1 failures.

    • 47.sram_ctrl_executable.14205620888306504159097324471843653378916662309403686645090937932459354593805
      Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/47.sram_ctrl_executable/latest/run.log

        UVM_FATAL @ 23163640485 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x971a67f0
        UVM_INFO @ 23163640485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.03.15_00.23.05
• 2024.03.13_04.19.00
• 2024.03.11_03.36.41
• 2024.03.08_05.24.35
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