SRAM_CTRL/MAIN Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: e6706fcc7b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.502m 808.552us 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.710s 46.470us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.730s 17.133us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.240s 190.534us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.720s 31.768us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 5.040s 3.827ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.730s 17.133us 20 20 100.00
sram_ctrl_csr_aliasing 0.720s 31.768us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 6.568m 128.155ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 3.139m 20.404ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 29.479m 21.312ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.491m 114.149ms 50 50 100.00
V2 bijection sram_ctrl_bijection 48.313m 220.712ms 49 50 98.00
V2 access_during_key_req sram_ctrl_access_during_key_req 45.287m 73.464ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 1.784m 73.153ms 50 50 100.00
V2 executable sram_ctrl_executable 43.666m 50.872ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.562m 997.378us 50 50 100.00
sram_ctrl_partial_access_b2b 10.723m 52.092ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.769m 766.771us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.738m 1.600ms 50 50 100.00
V2 regwen sram_ctrl_regwen 29.313m 22.413ms 49 50 98.00
V2 ram_cfg sram_ctrl_ram_cfg 4.560s 3.716ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.650h 211.506ms 50 50 100.00
V2 alert_test sram_ctrl_alert_test 0.750s 18.591us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.660s 155.591us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.660s 155.591us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.710s 46.470us 5 5 100.00
sram_ctrl_csr_rw 0.730s 17.133us 20 20 100.00
sram_ctrl_csr_aliasing 0.720s 31.768us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.830s 28.601us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.710s 46.470us 5 5 100.00
sram_ctrl_csr_rw 0.730s 17.133us 20 20 100.00
sram_ctrl_csr_aliasing 0.720s 31.768us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.830s 28.601us 20 20 100.00
V2 TOTAL 738 740 99.73
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 56.670s 29.380ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.720s 402.818us 5 5 100.00
sram_ctrl_tl_intg_err 2.520s 610.383us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.720s 402.818us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.520s 610.383us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 29.313m 22.413ms 49 50 98.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.730s 17.133us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 43.666m 50.872ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 43.666m 50.872ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 43.666m 50.872ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 1.784m 73.153ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 56.670s 29.380ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.502m 808.552us 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.502m 808.552us 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.502m 808.552us 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 43.666m 50.872ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.720s 402.818us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 1.784m 73.153ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.720s 402.818us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.720s 402.818us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.502m 808.552us 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.720s 402.818us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 4.736m 4.458ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1038 1040 99.81

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 14 87.50
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44

Failure Buckets

Past Results