SRAM_CTRL/MAIN Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: `4877b481e8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.696m	5.009ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.720s	17.522us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.690s	12.778us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.070s	1.274ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.730s	19.979us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.990s	4.412ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.690s	12.778us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	19.979us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.916m	199.484ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.966m	20.359ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	37.016m	58.565ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.612m	5.759ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	49.982m	550.504ms	48	50	96.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	30.077m	71.417ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.001m	18.617ms	50	50	100.00
V2	executable	sram_ctrl_executable	39.380m	25.944ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.451m	1.839ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.069m	113.512ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.635m	1.343ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.914m	2.233ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	44.641m	34.879ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.100s	4.199ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.467h	459.793ms	47	50	94.00
V2	alert_test	sram_ctrl_alert_test	0.720s	180.679us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.970s	143.428us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.970s	143.428us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.720s	17.522us	5	5	100.00
		sram_ctrl_csr_rw	0.690s	12.778us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	19.979us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	74.143us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.720s	17.522us	5	5	100.00
		sram_ctrl_csr_rw	0.690s	12.778us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	19.979us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	74.143us	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.006m	78.263ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.850s	359.012us	5	5	100.00
		sram_ctrl_tl_intg_err	2.490s	540.330us	19	20	95.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.850s	359.012us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.490s	540.330us	19	20	95.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	44.641m	34.879ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.690s	12.778us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	39.380m	25.944ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	39.380m	25.944ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	39.380m	25.944ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.001m	18.617ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.006m	78.263ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.696m	5.009ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.696m	5.009ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.696m	5.009ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	39.380m	25.944ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.850s	359.012us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.001m	18.617ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.850s	359.012us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.850s	359.012us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.696m	5.009ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.850s	359.012us	5	5	100.00
V2S		TOTAL			44	45	97.78
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.960m	12.826ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			1031	1040	99.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	3	3	2	66.67
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 2 failures:

Test sram_ctrl_stress_all has 2 failures.

4.sram_ctrl_stress_all.38283006660091011779623749035796534223662807273889724506300855266381907642909
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 894506233 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 894506233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.sram_ctrl_stress_all.35684498027292833436541370894087142275475492107657250130022847784412442649067
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 898748147 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 898748147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test sram_ctrl_bijection has 2 failures.
  - 19.sram_ctrl_bijection.18187668336021455177276745920082460458727763922375405854046388930937480974120
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.sram_ctrl_bijection.86920513090877363485234061837853071607262809501930715774005349278929192838015
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/30.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:839) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 2 failures.
  - 19.sram_ctrl_stress_all_with_rand_reset.62782877249078569916451029916974613001720776560816214354951239809080879374466
    Line 289, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1009903489 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1009903489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.sram_ctrl_stress_all_with_rand_reset.57577332002185098894006101174297462085365626794684473237535046874407123140525
    Line 347, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5151063969 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5151063969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job sram_ctrl_main-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 5.sram_ctrl_stress_all.24809767018132080512019550805958660187088969156485360829145749193276818939812
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_all/latest/run.log
```
  Job ID: smart:e36c97f5-46c2-4f9f-b277-19d0320f5d61
```
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
- Test sram_ctrl_tl_intg_err has 1 failures.
  - 19.sram_ctrl_tl_intg_err.27246290498040193680636047303898976132540521054816480113838365702510874448779
    Line 446, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_tl_intg_err/latest/run.log
```
  UVM_ERROR @ 298273528 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 298273528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 49.sram_ctrl_executable.11235761080107352641520086272196982673509930886899924053811781304424262136509
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/49.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 37148141612 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x9b96ceff
  UVM_INFO @ 37148141612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```