SRAM_CTRL/MAIN Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: 0bfa990ddc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.875m	16.921ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.690s	211.226us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.680s	121.263us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.600s	1.317ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.740s	29.152us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.710s	2.867ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.680s	121.263us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	29.152us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	7.322m	230.084ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.037m	5.594ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	48.238m	114.079ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.793m	11.580ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	44.648m	423.212ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	30.832m	92.976ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.804m	18.433ms	50	50	100.00
V2	executable	sram_ctrl_executable	38.697m	13.565ms	48	50	96.00
V2	partial_access	sram_ctrl_partial_access	3.254m	1.348ms	50	50	100.00
		sram_ctrl_partial_access_b2b	11.152m	29.341ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.606m	778.499us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.649m	828.220us	50	50	100.00
V2	regwen	sram_ctrl_regwen	42.929m	23.540ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.430s	3.063ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.341h	214.687ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	0.720s	75.311us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.840s	142.958us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.840s	142.958us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.690s	211.226us	5	5	100.00
		sram_ctrl_csr_rw	0.680s	121.263us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	29.152us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	28.381us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.690s	211.226us	5	5	100.00
		sram_ctrl_csr_rw	0.680s	121.263us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	29.152us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	28.381us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.052m	78.348ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.090s	341.891us	5	5	100.00
		sram_ctrl_tl_intg_err	2.970s	2.034ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.090s	341.891us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.970s	2.034ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	42.929m	23.540ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.680s	121.263us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	38.697m	13.565ms	48	50	96.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	38.697m	13.565ms	48	50	96.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	38.697m	13.565ms	48	50	96.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.804m	18.433ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.052m	78.348ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.875m	16.921ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.875m	16.921ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.875m	16.921ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	38.697m	13.565ms	48	50	96.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.090s	341.891us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.804m	18.433ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.090s	341.891us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.090s	341.891us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.875m	16.921ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.090s	341.891us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.448m	10.289ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1037	1040	99.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.92	99.19	94.27	99.72	100.00	96.03	99.12	97.07

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 2 failures:

  • Test sram_ctrl_executable has 2 failures.

    • 4.sram_ctrl_executable.45943650291608683649328781139508548549308748747452742192267880673089096379953
      Line 294, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_executable/latest/run.log

        UVM_FATAL @ 120954555166 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xee8725d0
        UVM_INFO @ 120954555166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 17.sram_ctrl_executable.113639215443932248120673118955373929523368661360624997172754630574312254859056
      Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_executable/latest/run.log

        UVM_FATAL @ 65760850259 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x8064745a
        UVM_INFO @ 65760850259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test sram_ctrl_bijection has 1 failures.

    • 49.sram_ctrl_bijection.32317053968479285339529906034293353389742392579385745660044472751262506934328
      Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/49.sram_ctrl_bijection/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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