SRAM_CTRL/MAIN Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	3.083m	819.898us	49	50	98.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.700s	18.088us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.730s	19.950us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.230s	162.914us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.780s	66.118us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	7.800s	10.012ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.730s	19.950us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	66.118us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.276m	82.638ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.958m	20.879ms	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	38.075m	135.449ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.008m	36.445ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	51.825m	172.263ms	48	50	96.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	34.670m	19.058ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.871m	122.336ms	50	50	100.00
V2	executable	sram_ctrl_executable	38.014m	13.721ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	3.563m	6.126ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.877m	51.182ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.850m	770.771us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.798m	3.549ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	27.280m	30.821ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.640s	3.744ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.631h	309.837ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	0.710s	16.472us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.000s	263.360us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.000s	263.360us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.700s	18.088us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	19.950us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	66.118us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.880s	128.229us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.700s	18.088us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	19.950us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	66.118us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.880s	128.229us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	59.510s	29.413ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.410s	269.467us	5	5	100.00
		sram_ctrl_tl_intg_err	2.580s	278.133us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.410s	269.467us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.580s	278.133us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	27.280m	30.821ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.730s	19.950us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	38.014m	13.721ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	38.014m	13.721ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	38.014m	13.721ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.871m	122.336ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	59.510s	29.413ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	3.083m	819.898us	49	50	98.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	3.083m	819.898us	49	50	98.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	3.083m	819.898us	49	50	98.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	38.014m	13.721ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.410s	269.467us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.871m	122.336ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.410s	269.467us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.410s	269.467us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	3.083m	819.898us	49	50	98.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.410s	269.467us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	5.927m	1.287ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			1033	1040	99.33

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	6	75.00
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test sram_ctrl_bijection has 2 failures.
  - 2.sram_ctrl_bijection.110072132271962267179406837210146696151057479486482478803513607720754848513709
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.sram_ctrl_bijection.39383374897249971592894151978991405137320710553149903835446231593258067478098
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (sram_ctrl_base_vseq.sv:149) [sram_ctrl_common_vseq] Timed out waiting for initialization done has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 13.sram_ctrl_csr_mem_rw_with_rand_reset.113560633361807282392031734964358689234129629717943672483990365098532842873535
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10012482277 ps: (sram_ctrl_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Timed out waiting for initialization done
  UVM_INFO @ 10012482277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_smoke has 1 failures.
  - 20.sram_ctrl_smoke.37613306567632992528142190305823664885155515240577149170733191364791830456338
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 20997235539 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xc872910
  UVM_INFO @ 20997235539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:839) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 32.sram_ctrl_stress_all_with_rand_reset.75661222937921421030523218239214442958994999440151962589725509341618836518812
    Line 291, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2031090444 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2031090444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:758) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 38.sram_ctrl_stress_all_with_rand_reset.23419122965994677825640498112895576793046535061158868637933808536253093860878
    Line 450, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3085001089 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3085001089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 49.sram_ctrl_stress_all.55298228853553156138720124752730555631778854686223831360542891273524437424728
    Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 15524430700 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xc1b536bb
  UVM_INFO @ 15524430700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/MAIN Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e971cd9798`