SRAM_CTRL/MAIN Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.536m	1.881ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.710s	45.471us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.700s	21.190us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.450s	178.632us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.760s	59.752us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.460s	930.427us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.700s	21.190us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	59.752us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.896m	179.216ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.025m	5.243ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	34.810m	69.907ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.550m	22.582ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	50.650m	689.376ms	47	50	94.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	35.721m	74.979ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.367m	305.024ms	50	50	100.00
V2	executable	sram_ctrl_executable	30.855m	82.002ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	3.288m	892.189us	50	50	100.00
		sram_ctrl_partial_access_b2b	10.194m	115.373ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.828m	3.055ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.609m	821.640us	50	50	100.00
V2	regwen	sram_ctrl_regwen	30.461m	34.865ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.200s	2.250ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.724h	430.604ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	0.720s	94.468us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.190s	528.891us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.190s	528.891us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.710s	45.471us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	21.190us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	59.752us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.840s	120.231us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.710s	45.471us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	21.190us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	59.752us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.840s	120.231us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.196m	117.569ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.230s	280.726us	5	5	100.00
		sram_ctrl_tl_intg_err	3.440s	683.928us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.230s	280.726us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.440s	683.928us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	30.461m	34.865ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.700s	21.190us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	30.855m	82.002ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	30.855m	82.002ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	30.855m	82.002ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.367m	305.024ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.196m	117.569ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.536m	1.881ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.536m	1.881ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.536m	1.881ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	30.855m	82.002ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.230s	280.726us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.367m	305.024ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.230s	280.726us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.230s	280.726us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.536m	1.881ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.230s	280.726us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.772m	2.842ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1035	1040	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.99	99.19	94.27	99.72	100.00	96.03	99.12	97.62

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test sram_ctrl_bijection has 3 failures.
  - 4.sram_ctrl_bijection.90650425189282366302156176175647591582277952581476548588882832104435781099243
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.sram_ctrl_bijection.33874421208590158306051284547212902582515842850318120644122028651192961002026
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/25.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:839) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 0.sram_ctrl_stress_all_with_rand_reset.4174123371519368698592414399016624046123109315215671144884620631056524712670
    Line 315, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6334587745 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6334587745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 25.sram_ctrl_stress_all.102946218270636042984782254261280492544769564793678812836870551336477862056548
    Line 441, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 886188762962 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xc65f7797
  UVM_INFO @ 886188762962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/MAIN Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e971cd9798`