SRAM_CTRL/MAIN Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.675m 3.941ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.750s 21.468us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.690s 21.887us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.380s 339.807us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.740s 21.462us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 4.420s 4.397ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.690s 21.887us 20 20 100.00
sram_ctrl_csr_aliasing 0.740s 21.462us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 6.268m 114.965ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 3.014m 32.657ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 41.185m 115.074ms 49 50 98.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.974m 7.874ms 50 50 100.00
V2 bijection sram_ctrl_bijection 51.788m 143.643ms 49 50 98.00
V2 access_during_key_req sram_ctrl_access_during_key_req 28.814m 14.639ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 2.236m 83.092ms 50 50 100.00
V2 executable sram_ctrl_executable 39.366m 123.860ms 46 50 92.00
V2 partial_access sram_ctrl_partial_access 2.594m 15.623ms 50 50 100.00
sram_ctrl_partial_access_b2b 9.688m 36.724ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.903m 1.868ms 50 50 100.00
sram_ctrl_throughput_w_partial_write 3.010m 3.389ms 50 50 100.00
V2 regwen sram_ctrl_regwen 36.613m 24.004ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 4.900s 4.775ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.272h 2.715s 49 50 98.00
V2 alert_test sram_ctrl_alert_test 0.720s 25.017us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.690s 544.802us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.690s 544.802us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.750s 21.468us 5 5 100.00
sram_ctrl_csr_rw 0.690s 21.887us 20 20 100.00
sram_ctrl_csr_aliasing 0.740s 21.462us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.870s 59.813us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.750s 21.468us 5 5 100.00
sram_ctrl_csr_rw 0.690s 21.887us 20 20 100.00
sram_ctrl_csr_aliasing 0.740s 21.462us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.870s 59.813us 20 20 100.00
V2 TOTAL 733 740 99.05
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 1.051m 29.352ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.300s 259.805us 5 5 100.00
sram_ctrl_tl_intg_err 2.990s 602.674us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.300s 259.805us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.990s 602.674us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 36.613m 24.004ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.690s 21.887us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 39.366m 123.860ms 46 50 92.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 39.366m 123.860ms 46 50 92.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 39.366m 123.860ms 46 50 92.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 2.236m 83.092ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 1.051m 29.352ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.675m 3.941ms 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.675m 3.941ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.675m 3.941ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 39.366m 123.860ms 46 50 92.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.300s 259.805us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 2.236m 83.092ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.300s 259.805us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.300s 259.805us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.675m 3.941ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.300s 259.805us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 4.947m 3.967ms 49 50 98.00
V3 TOTAL 49 50 98.00
TOTAL 1032 1040 99.23

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 12 75.00
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44

Failure Buckets

Past Results