SRAM_CTRL/MAIN Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: 3e0219a2c5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.927m 1.046ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.710s 27.197us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.730s 62.576us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.040s 244.841us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.760s 78.023us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 4.880s 3.198ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.730s 62.576us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 78.023us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 6.393m 69.114ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 3.155m 98.233ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 41.308m 32.097ms 49 50 98.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.426m 6.353ms 50 50 100.00
V2 bijection sram_ctrl_bijection 47.694m 574.315ms 47 50 94.00
V2 access_during_key_req sram_ctrl_access_during_key_req 30.541m 83.181ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 2.449m 76.554ms 50 50 100.00
V2 executable sram_ctrl_executable 38.344m 94.320ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.798m 961.840us 50 50 100.00
sram_ctrl_partial_access_b2b 12.062m 118.235ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.977m 4.029ms 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.836m 3.187ms 50 50 100.00
V2 regwen sram_ctrl_regwen 51.771m 36.425ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 4.920s 4.765ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.262h 268.785ms 48 50 96.00
V2 alert_test sram_ctrl_alert_test 0.730s 43.309us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.720s 1.029ms 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.720s 1.029ms 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.710s 27.197us 5 5 100.00
sram_ctrl_csr_rw 0.730s 62.576us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 78.023us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.790s 33.732us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.710s 27.197us 5 5 100.00
sram_ctrl_csr_rw 0.730s 62.576us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 78.023us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.790s 33.732us 20 20 100.00
V2 TOTAL 734 740 99.19
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 1.051m 29.392ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.650s 621.434us 5 5 100.00
sram_ctrl_tl_intg_err 2.560s 1.250ms 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.650s 621.434us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.560s 1.250ms 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 51.771m 36.425ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.730s 62.576us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 38.344m 94.320ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 38.344m 94.320ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 38.344m 94.320ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 2.449m 76.554ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 1.051m 29.392ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.927m 1.046ms 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.927m 1.046ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.927m 1.046ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 38.344m 94.320ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.650s 621.434us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 2.449m 76.554ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.650s 621.434us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.650s 621.434us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.927m 1.046ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.650s 621.434us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 3.844m 9.994ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1034 1040 99.42

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 13 81.25
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44

Failure Buckets

Past Results