SRAM_CTRL/MAIN Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: e439226b6c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.558m 776.947us 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.730s 30.872us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.710s 15.094us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 1.960s 157.730us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.760s 91.802us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 6.350s 10.010ms 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.710s 15.094us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 91.802us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 6.102m 20.724ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 3.066m 20.899ms 50 50 100.00
V1 TOTAL 204 205 99.51
V2 multiple_keys sram_ctrl_multiple_keys 43.471m 65.237ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.347m 7.296ms 50 50 100.00
V2 bijection sram_ctrl_bijection 50.795m 317.221ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 37.221m 43.835ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 2.344m 175.850ms 50 50 100.00
V2 executable sram_ctrl_executable 35.148m 65.269ms 49 50 98.00
V2 partial_access sram_ctrl_partial_access 2.614m 874.798us 50 50 100.00
sram_ctrl_partial_access_b2b 10.548m 251.185ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.400m 1.624ms 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.894m 820.674us 50 50 100.00
V2 regwen sram_ctrl_regwen 39.615m 98.857ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 5.640s 6.739ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.374h 737.777ms 46 50 92.00
V2 alert_test sram_ctrl_alert_test 0.730s 23.749us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.060s 149.587us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.060s 149.587us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.730s 30.872us 5 5 100.00
sram_ctrl_csr_rw 0.710s 15.094us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 91.802us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.820s 25.265us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.730s 30.872us 5 5 100.00
sram_ctrl_csr_rw 0.710s 15.094us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 91.802us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.820s 25.265us 20 20 100.00
V2 TOTAL 735 740 99.32
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 55.670s 14.392ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.360s 452.851us 5 5 100.00
sram_ctrl_tl_intg_err 3.640s 677.086us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.360s 452.851us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 3.640s 677.086us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 39.615m 98.857ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.710s 15.094us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 35.148m 65.269ms 49 50 98.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 35.148m 65.269ms 49 50 98.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 35.148m 65.269ms 49 50 98.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 2.344m 175.850ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 55.670s 14.392ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.558m 776.947us 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.558m 776.947us 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.558m 776.947us 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 35.148m 65.269ms 49 50 98.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.360s 452.851us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 2.344m 175.850ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.360s 452.851us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.360s 452.851us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.558m 776.947us 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.360s 452.851us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 4.868m 6.679ms 48 50 96.00
V3 TOTAL 48 50 96.00
TOTAL 1032 1040 99.23

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 16 14 87.50
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44

Failure Buckets

Past Results