SRAM_CTRL/MAIN Simulation Results

Saturday July 27 2024 23:02:25 UTC

GitHub Revision: eca25c0ff8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6528518538521148567139195500524222710943459299328477504124649113671643189924

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.850m	824.412us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.750s	49.059us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.710s	21.416us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.840s	330.132us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.770s	34.617us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.810s	1.462ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.710s	21.416us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	34.617us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.814m	197.213ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.261m	61.177ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	42.906m	109.841ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.386m	5.676ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	46.669m	170.557ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	32.209m	14.664ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.846m	48.907ms	50	50	100.00
V2	executable	sram_ctrl_executable	27.386m	50.208ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.424m	2.781ms	50	50	100.00
		sram_ctrl_partial_access_b2b	11.113m	29.605ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.759m	2.727ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.793m	824.644us	50	50	100.00
V2	regwen	sram_ctrl_regwen	40.357m	16.259ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.220s	2.591ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.668h	278.422ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	0.690s	16.213us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.040s	297.063us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.040s	297.063us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.750s	49.059us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	21.416us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	34.617us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.920s	71.220us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.750s	49.059us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	21.416us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	34.617us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.920s	71.220us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	57.180s	14.693ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.160s	957.797us	5	5	100.00
		sram_ctrl_tl_intg_err	3.950s	3.576ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.160s	957.797us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.950s	3.576ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	40.357m	16.259ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.710s	21.416us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	27.386m	50.208ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	27.386m	50.208ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	27.386m	50.208ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.846m	48.907ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	57.180s	14.693ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.850m	824.412us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.850m	824.412us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.850m	824.412us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	27.386m	50.208ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.160s	957.797us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.846m	48.907ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.160s	957.797us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.160s	957.797us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.850m	824.412us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.160s	957.797us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.208m	5.520ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1038	1040	99.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.99	99.19	94.27	99.72	100.00	96.03	99.12	97.62

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test sram_ctrl_bijection has 1 failures.

    • 36.sram_ctrl_bijection.70993967750848108118257313267394088619305530307684089996423997076913488915390
      Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/36.sram_ctrl_bijection/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_stress_all has 1 failures.

    • 45.sram_ctrl_stress_all.12615957330174695872883442089351818666422504212961732387332362051143415245157
      Line 386, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 396553552062 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xc975d31d
        UVM_INFO @ 396553552062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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