SRAM_CTRL/MAIN Simulation Results

Sunday July 28 2024 23:02:28 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 35694793988142953409419697382868702825984401131209466119932029294128690866559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.439m	777.354us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.720s	41.846us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.700s	14.797us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.380s	589.641us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.730s	20.011us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	10.930s	10.006ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.700s	14.797us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	20.011us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.398m	82.657ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.819m	9.646ms	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	28.066m	25.928ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.769m	23.673ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	44.245m	112.741ms	48	50	96.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	36.246m	17.955ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.144m	90.506ms	50	50	100.00
V2	executable	sram_ctrl_executable	40.006m	28.650ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.524m	3.950ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.273m	28.584ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.715m	1.539ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.511m	3.269ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	32.230m	25.927ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.940s	3.724ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.464h	679.257ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	0.740s	22.471us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.070s	45.029us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.070s	45.029us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.720s	41.846us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	14.797us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	20.011us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.860s	95.196us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.720s	41.846us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	14.797us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	20.011us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.860s	95.196us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.022m	44.136ms	19	20	95.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.110s	859.832us	5	5	100.00
		sram_ctrl_tl_intg_err	2.780s	1.488ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.110s	859.832us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.780s	1.488ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	32.230m	25.927ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.700s	14.797us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	40.006m	28.650ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	40.006m	28.650ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	40.006m	28.650ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.144m	90.506ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.022m	44.136ms	19	20	95.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.439m	777.354us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.439m	777.354us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.439m	777.354us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	40.006m	28.650ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.110s	859.832us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.144m	90.506ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.110s	859.832us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.110s	859.832us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.439m	777.354us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.110s	859.832us	5	5	100.00
V2S		TOTAL			44	45	97.78
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.951m	2.368ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1033	1040	99.33

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	13	81.25
V2S	3	3	2	66.67
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.99	99.19	94.27	99.72	100.00	96.03	99.12	97.62

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test sram_ctrl_bijection has 2 failures.
  - 35.sram_ctrl_bijection.19750588240311452230115911729679651054398451853200763296402980302183416474293
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/35.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.sram_ctrl_bijection.10156954026102828812127757025176457785098085653058428672964067842275750719949
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/36.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (sram_ctrl_base_vseq.sv:149) [sram_ctrl_common_vseq] Timed out waiting for initialization done has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 11.sram_ctrl_csr_mem_rw_with_rand_reset.10398228281953866025583779557879985875132688907769687447684788189601410052341
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10006113519 ps: (sram_ctrl_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Timed out waiting for initialization done
  UVM_INFO @ 10006113519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
- Test sram_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 13.sram_ctrl_passthru_mem_tl_intg_err.58794323112117297773363295393092911257334870640655245855247419351214838917986
    Line 333, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_ERROR @ 12105461424 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 12105461424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(rdata_o))' has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 15.sram_ctrl_stress_all.95971864984701149312312526983873245186801195106588123267695526570406555716381
    Line 282, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_all/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @ 4028048094 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @ 4028048094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:839) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 34.sram_ctrl_stress_all_with_rand_reset.69294862121477842753882404855328716263872456179170462137339217664871301692805
    Line 330, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2263913782 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2263913782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 38.sram_ctrl_executable.26833591193218435393024251149394187889567544001200278668585671139648408275103
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/38.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 40397573067 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x5c93c41d
  UVM_INFO @ 40397573067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/MAIN Simulation Results

Sunday July 28 2024 23:02:28 UTC

GitHub Revision: eca25c0ff8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 35694793988142953409419697382868702825984401131209466119932029294128690866559

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `eca25c0ff8`