SRAM_CTRL/MAIN Simulation Results

Monday July 29 2024 23:02:32 UTC

GitHub Revision: 39f3866b56

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 91682663165753342493852681547271085771042321116470426223748766059309541455602

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.407m 5.224ms 49 50 98.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.700s 20.115us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.750s 18.682us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 1.770s 51.236us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.730s 80.989us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 5.710s 736.493us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.750s 18.682us 20 20 100.00
sram_ctrl_csr_aliasing 0.730s 80.989us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 6.174m 78.059ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 3.045m 20.038ms 50 50 100.00
V1 TOTAL 204 205 99.51
V2 multiple_keys sram_ctrl_multiple_keys 30.873m 33.120ms 48 50 96.00
V2 stress_pipeline sram_ctrl_stress_pipeline 8.316m 7.376ms 50 50 100.00
V2 bijection sram_ctrl_bijection 47.873m 234.640ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 27.726m 57.654ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 1.823m 231.942ms 50 50 100.00
V2 executable sram_ctrl_executable 31.765m 126.288ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.494m 16.570ms 50 50 100.00
sram_ctrl_partial_access_b2b 10.648m 100.403ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.814m 9.512ms 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.687m 821.871us 50 50 100.00
V2 regwen sram_ctrl_regwen 31.707m 20.554ms 49 50 98.00
V2 ram_cfg sram_ctrl_ram_cfg 3.750s 1.404ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.506h 51.710ms 48 50 96.00
V2 alert_test sram_ctrl_alert_test 0.720s 13.317us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.130s 580.735us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.130s 580.735us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.700s 20.115us 5 5 100.00
sram_ctrl_csr_rw 0.750s 18.682us 20 20 100.00
sram_ctrl_csr_aliasing 0.730s 80.989us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.860s 151.119us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.700s 20.115us 5 5 100.00
sram_ctrl_csr_rw 0.750s 18.682us 20 20 100.00
sram_ctrl_csr_aliasing 0.730s 80.989us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.860s 151.119us 20 20 100.00
V2 TOTAL 735 740 99.32
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 1.394m 100.688ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.180s 344.660us 5 5 100.00
sram_ctrl_tl_intg_err 2.610s 282.618us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.180s 344.660us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.610s 282.618us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 31.707m 20.554ms 49 50 98.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.750s 18.682us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 31.765m 126.288ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 31.765m 126.288ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 31.765m 126.288ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 1.823m 231.942ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 1.394m 100.688ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.407m 5.224ms 49 50 98.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.407m 5.224ms 49 50 98.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.407m 5.224ms 49 50 98.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 31.765m 126.288ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.180s 344.660us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 1.823m 231.942ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.180s 344.660us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.180s 344.660us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.407m 5.224ms 49 50 98.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.180s 344.660us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 2.874m 10.759ms 48 50 96.00
V3 TOTAL 48 50 96.00
TOTAL 1032 1040 99.23

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 16 13 81.25
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44

Failure Buckets

Past Results