SRAM_CTRL/MAIN Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: `fdfa12db04`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.351m	782.691us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.710s	22.286us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.730s	15.182us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.400s	2.822ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.760s	14.278us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.880s	376.712us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.730s	15.182us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	14.278us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	7.339m	258.728ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.978m	26.406ms	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	32.560m	102.815ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.640m	23.812ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	47.138m	442.473ms	48	50	96.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	33.225m	92.626ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.854m	38.128ms	50	50	100.00
V2	executable	sram_ctrl_executable	28.445m	39.172ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.755m	8.303ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.579m	54.805ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.580m	9.521ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.496m	4.279ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	29.316m	18.635ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.110s	3.739ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.962h	1.479s	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	0.770s	16.219us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.880s	565.639us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.880s	565.639us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.710s	22.286us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	15.182us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	14.278us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.860s	258.397us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.710s	22.286us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	15.182us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	14.278us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.860s	258.397us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.482m	117.499ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.260s	978.891us	5	5	100.00
		sram_ctrl_tl_intg_err	3.380s	780.843us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.260s	978.891us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.380s	780.843us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	29.316m	18.635ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.730s	15.182us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	28.445m	39.172ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	28.445m	39.172ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	28.445m	39.172ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.854m	38.128ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.482m	117.499ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.351m	782.691us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.351m	782.691us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.351m	782.691us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	28.445m	39.172ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.260s	978.891us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.854m	38.128ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.260s	978.891us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.260s	978.891us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.351m	782.691us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.260s	978.891us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.887m	8.888ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1034	1040	99.42

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test sram_ctrl_bijection has 2 failures.
  - 14.sram_ctrl_bijection.91170298622072617050269734844720082131716288669634175339284294589735636462726
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.sram_ctrl_bijection.95489594514879347696259989027656863905656491810234088588949536997045150731392
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/22.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:836) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 7.sram_ctrl_stress_all_with_rand_reset.47339015725330240850208165746634102912311296586537906397145350060112278709558
    Line 347, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9710772242 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9710772242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:264) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 8.sram_ctrl_regwen.91232489242309819542115021882754691308157168059378872292950138487546408730323
    Line 288, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 70378064852 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xae2ae410
  UVM_INFO @ 70378064852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:755) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 15.sram_ctrl_csr_mem_rw_with_rand_reset.78988519771997209364280901227069327413919015068587633399594447583237689872461
    Line 272, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1344989702 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1344989702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job sram_ctrl_main-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 28.sram_ctrl_stress_all.65324664400098599037975727820949248516196719397283113486095641827562466851524
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_all/latest/run.log
```
  Job ID: smart:6c1ba570-6ad0-40b7-a262-20f48d3d6bb6
```

SRAM_CTRL/MAIN Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: fdfa12db04

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `fdfa12db04`