SRAM_CTRL/MAIN Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: e9b7e615a7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.440m 780.547us 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.700s 23.803us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.750s 14.039us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.150s 511.223us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.790s 21.153us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 9.870s 10.008ms 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.750s 14.039us 20 20 100.00
sram_ctrl_csr_aliasing 0.790s 21.153us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 6.267m 276.676ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 3.134m 10.701ms 50 50 100.00
V1 TOTAL 204 205 99.51
V2 multiple_keys sram_ctrl_multiple_keys 41.992m 30.983ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.165m 97.234ms 50 50 100.00
V2 bijection sram_ctrl_bijection 54.248m 718.509ms 48 50 96.00
V2 access_during_key_req sram_ctrl_access_during_key_req 36.631m 40.883ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 2.323m 76.420ms 50 50 100.00
V2 executable sram_ctrl_executable 35.431m 39.346ms 49 50 98.00
V2 partial_access sram_ctrl_partial_access 2.609m 3.088ms 50 50 100.00
sram_ctrl_partial_access_b2b 9.552m 229.894ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.519m 3.475ms 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.491m 3.131ms 50 50 100.00
V2 regwen sram_ctrl_regwen 30.842m 45.473ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 4.390s 6.736ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.354h 378.862ms 48 50 96.00
V2 alert_test sram_ctrl_alert_test 0.720s 19.709us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.000s 255.072us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.000s 255.072us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.700s 23.803us 5 5 100.00
sram_ctrl_csr_rw 0.750s 14.039us 20 20 100.00
sram_ctrl_csr_aliasing 0.790s 21.153us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.870s 24.371us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.700s 23.803us 5 5 100.00
sram_ctrl_csr_rw 0.750s 14.039us 20 20 100.00
sram_ctrl_csr_aliasing 0.790s 21.153us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.870s 24.371us 20 20 100.00
V2 TOTAL 735 740 99.32
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 56.190s 28.199ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.590s 3.116ms 5 5 100.00
sram_ctrl_tl_intg_err 3.120s 1.762ms 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.590s 3.116ms 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 3.120s 1.762ms 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 30.842m 45.473ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.750s 14.039us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 35.431m 39.346ms 49 50 98.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 35.431m 39.346ms 49 50 98.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 35.431m 39.346ms 49 50 98.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 2.323m 76.420ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 56.190s 28.199ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.440m 780.547us 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.440m 780.547us 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.440m 780.547us 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 35.431m 39.346ms 49 50 98.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.590s 3.116ms 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 2.323m 76.420ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.590s 3.116ms 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.590s 3.116ms 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.440m 780.547us 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.590s 3.116ms 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 3.885m 10.878ms 48 50 96.00
V3 TOTAL 48 50 96.00
TOTAL 1032 1040 99.23

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 16 13 81.25
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.92 99.19 94.15 99.72 100.00 95.79 99.12 97.44

Failure Buckets

Past Results