SRAM_CTRL/MAIN Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: `625f353e9c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.450m	3.104ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.740s	19.589us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.720s	41.009us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.870s	161.002us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.770s	201.330us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	16.890s	10.003ms	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.720s	41.009us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	201.330us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.010m	295.557ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.178m	12.920ms	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	27.517m	104.462ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.193m	5.904ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	46.789m	166.063ms	46	50	92.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	29.314m	32.303ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.048m	90.609ms	50	50	100.00
V2	executable	sram_ctrl_executable	35.752m	85.008ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.767m	1.422ms	50	50	100.00
		sram_ctrl_partial_access_b2b	11.182m	40.231ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.741m	5.102ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.741m	2.004ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	34.571m	39.980ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.160s	3.053ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.867h	176.759ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	0.710s	16.515us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.590s	634.140us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.590s	634.140us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.740s	19.589us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	41.009us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	201.330us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	23.869us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.740s	19.589us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	41.009us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	201.330us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	23.869us	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.126m	58.740ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.850s	171.155us	5	5	100.00
		sram_ctrl_tl_intg_err	2.790s	1.497ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.850s	171.155us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.790s	1.497ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	34.571m	39.980ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.720s	41.009us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	35.752m	85.008ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	35.752m	85.008ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	35.752m	85.008ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.048m	90.609ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.126m	58.740ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.450m	3.104ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.450m	3.104ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.450m	3.104ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	35.752m	85.008ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.850s	171.155us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.048m	90.609ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.850s	171.155us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.850s	171.155us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.450m	3.104ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.850s	171.155us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	5.025m	42.691ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1031	1040	99.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test sram_ctrl_bijection has 4 failures.
  - 2.sram_ctrl_bijection.17055258655793791051226691819706412484033058605268072663497618217084876687178
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.sram_ctrl_bijection.59512798923553139969929370085835210481710384328843573496028869565623577430566
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (sram_ctrl_base_vseq.sv:149) [sram_ctrl_common_vseq] Timed out waiting for initialization done has 2 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 5.sram_ctrl_csr_mem_rw_with_rand_reset.7980897266858487879050909896013498148681367891814990646050693134936428603155
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10002846728 ps: (sram_ctrl_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Timed out waiting for initialization done
  UVM_INFO @ 10002846728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.sram_ctrl_csr_mem_rw_with_rand_reset.46224382234253728747600442753271107916542735679370928327356924697192231781933
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10012418186 ps: (sram_ctrl_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Timed out waiting for initialization done
  UVM_INFO @ 10012418186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:264) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 9.sram_ctrl_multiple_keys.60528575320504423043946421186371056618689243145191868374953296916501898142180
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 23193875019 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x9c3db5cf
  UVM_INFO @ 23193875019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:264) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 27.sram_ctrl_stress_all.73728157576301180305719423649945791480033747114001118274044416731784084199462
    Line 281, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 25233319170 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x850e5ccd
  UVM_INFO @ 25233319170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:836) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 40.sram_ctrl_stress_all_with_rand_reset.42835988212559220082667909911031366359093057910727724917916675001245384858523
    Line 323, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/40.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5698546352 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5698546352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/MAIN Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: 625f353e9c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `625f353e9c`