SRAM_CTRL/MAIN Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: `5fd4ecc0fc`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	3.002m	1.351ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.730s	73.267us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.710s	23.704us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.230s	1.149ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.770s	15.565us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.320s	1.495ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.710s	23.704us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	15.565us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.200m	137.963ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.325m	24.156ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	26.543m	78.859ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.796m	7.848ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	43.750m	526.346ms	47	50	94.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	43.826m	84.289ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.793m	91.065ms	49	50	98.00
V2	executable	sram_ctrl_executable	33.097m	348.816ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.938m	7.536ms	50	50	100.00
		sram_ctrl_partial_access_b2b	11.856m	119.865ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.886m	4.480ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	3.285m	3.716ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	25.188m	36.269ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.420s	6.707ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.222h	831.995ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	0.720s	11.579us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.750s	536.771us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.750s	536.771us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.730s	73.267us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	23.704us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	15.565us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.840s	47.915us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.730s	73.267us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	23.704us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	15.565us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.840s	47.915us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.108m	37.087ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.380s	339.267us	5	5	100.00
		sram_ctrl_tl_intg_err	3.350s	616.060us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.380s	339.267us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.350s	616.060us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	25.188m	36.269ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.710s	23.704us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	33.097m	348.816ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	33.097m	348.816ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	33.097m	348.816ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.793m	91.065ms	49	50	98.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.108m	37.087ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	3.002m	1.351ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	3.002m	1.351ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	3.002m	1.351ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	33.097m	348.816ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.380s	339.267us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.793m	91.065ms	49	50	98.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.380s	339.267us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.380s	339.267us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	3.002m	1.351ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.380s	339.267us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.013m	3.162ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			1033	1040	99.33

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test sram_ctrl_bijection has 3 failures.
  - 13.sram_ctrl_bijection.35699885315531594473995150696093492463385678999261954577242695412481327240595
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.sram_ctrl_bijection.34150161004840622712492677644641893204628298818047651422275450057076924668837
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 2 failures.
  - 39.sram_ctrl_stress_all_with_rand_reset.27672292090721768582898183969218501011963599512408932947150400179654141639554
    Line 348, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3161838434 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3161838434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.sram_ctrl_stress_all_with_rand_reset.32219255420884322420382852119900724825886050626882612604678076484462909706323
    Line 325, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7175833522 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7175833522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (mem_model.sv:48) [exp_mem_sram_ctrl_prim_reg_block] Check failed act_data === system_memory[addr] (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test sram_ctrl_lc_escalation has 1 failures.
  - 8.sram_ctrl_lc_escalation.56383447775091295336276771772801742524152476966571230817580760995921805536995
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_lc_escalation/latest/run.log
```
  UVM_ERROR @ 4929117099 ps: (mem_model.sv:48) [exp_mem_sram_ctrl_prim_reg_block] Check failed act_data === system_memory[addr] (0x79 [1111001] vs 0xbf [10111111]) addr 0x2eda55fc read out mismatch
  UVM_INFO @ 4929117099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:264) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 46.sram_ctrl_executable.57957246960121554539445555089145515523954414168392493917498026002471324955997
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/46.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 32599581782 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x4b89e0d
  UVM_INFO @ 32599581782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/MAIN Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: 5fd4ecc0fc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `5fd4ecc0fc`