SRAM_CTRL/MAIN Simulation Results

Friday August 02 2024 23:02:48 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75989420798843487383163268541581889763599806834398027919895759109584083292465

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.402m 2.597ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.710s 92.244us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.710s 23.345us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.210s 129.690us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.770s 83.255us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 5.060s 2.889ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.710s 23.345us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 83.255us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 6.762m 66.447ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 3.009m 5.798ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 40.641m 58.763ms 49 50 98.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.090m 91.715ms 50 50 100.00
V2 bijection sram_ctrl_bijection 46.608m 736.898ms 47 50 94.00
V2 access_during_key_req sram_ctrl_access_during_key_req 28.709m 101.745ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 2.122m 69.797ms 50 50 100.00
V2 executable sram_ctrl_executable 40.922m 101.130ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.881m 7.263ms 50 50 100.00
sram_ctrl_partial_access_b2b 9.846m 23.257ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.607m 1.600ms 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.847m 3.121ms 50 50 100.00
V2 regwen sram_ctrl_regwen 37.423m 19.495ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 4.310s 3.053ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.867h 533.256ms 47 50 94.00
V2 alert_test sram_ctrl_alert_test 0.740s 13.403us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.130s 615.546us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.130s 615.546us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.710s 92.244us 5 5 100.00
sram_ctrl_csr_rw 0.710s 23.345us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 83.255us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.820s 22.877us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.710s 92.244us 5 5 100.00
sram_ctrl_csr_rw 0.710s 23.345us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 83.255us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.820s 22.877us 20 20 100.00
V2 TOTAL 733 740 99.05
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 59.990s 100.658ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.200s 324.403us 5 5 100.00
sram_ctrl_tl_intg_err 3.200s 2.505ms 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.200s 324.403us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 3.200s 2.505ms 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 37.423m 19.495ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.710s 23.345us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 40.922m 101.130ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 40.922m 101.130ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 40.922m 101.130ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 2.122m 69.797ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 59.990s 100.658ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.402m 2.597ms 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.402m 2.597ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.402m 2.597ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 40.922m 101.130ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.200s 324.403us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 2.122m 69.797ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.200s 324.403us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.200s 324.403us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.402m 2.597ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.200s 324.403us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 4.573m 7.557ms 49 50 98.00
V3 TOTAL 49 50 98.00
TOTAL 1032 1040 99.23

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 13 81.25
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.99 99.19 94.27 99.72 100.00 96.03 99.12 97.62

Failure Buckets

Past Results