SRAM_CTRL/MAIN Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.543m	2.752ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.740s	45.774us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.740s	13.459us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.770s	47.355us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.770s	45.844us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.840s	1.837ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.740s	13.459us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	45.844us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.532m	187.988ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.954m	5.012ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	44.069m	70.239ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.183m	57.398ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	43.534m	225.104ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	45.546m	80.858ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.002m	37.192ms	50	50	100.00
V2	executable	sram_ctrl_executable	45.471m	15.283ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.467m	4.661ms	50	50	100.00
		sram_ctrl_partial_access_b2b	11.395m	111.659ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.934m	6.948ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.720m	3.404ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	33.420m	15.863ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.210s	4.167ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.936h	923.400ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	0.690s	21.786us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.830s	137.888us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.830s	137.888us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.740s	45.774us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	13.459us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	45.844us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.850s	100.718us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.740s	45.774us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	13.459us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	45.844us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.850s	100.718us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.012m	29.334ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	5.170s	1.320ms	5	5	100.00
		sram_ctrl_tl_intg_err	2.390s	259.671us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	5.170s	1.320ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.390s	259.671us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	33.420m	15.863ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.740s	13.459us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	45.471m	15.283ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	45.471m	15.283ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	45.471m	15.283ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.002m	37.192ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.012m	29.334ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.543m	2.752ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.543m	2.752ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.543m	2.752ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	45.471m	15.283ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	5.170s	1.320ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.002m	37.192ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	5.170s	1.320ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	5.170s	1.320ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.543m	2.752ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	5.170s	1.320ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	6.555m	9.675ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1038	1040	99.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.94	99.19	94.27	99.72	100.00	96.03	99.12	97.26

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test sram_ctrl_bijection has 1 failures.

    • 6.sram_ctrl_bijection.17206525344914701994956774988407697113669492813909235942766515651381916843734
      Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_bijection/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:264) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_stress_all has 1 failures.

    • 34.sram_ctrl_stress_all.81260834242340776227829894107332924540031593168472000756762545023150154882839
      Line 291, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 81287693487 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xa719dc88
        UVM_INFO @ 81287693487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.04_06.58.43
• 2024.08.03_09.10.27
• 2024.08.02_08.22.50
• 2024.08.01_09.50.08
• 2024.07.31_09.17.41
• 2024.07.30_09.36.29
• 2024.07.29_08.01.37