SRAM_CTRL/MAIN Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.779m	1.057ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.730s	44.197us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.740s	81.850us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.280s	685.042us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.780s	17.133us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.900s	4.332ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.740s	81.850us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	17.133us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.261m	114.890ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.061m	34.981ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	31.111m	54.195ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.082m	16.537ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	50.970m	344.848ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	32.627m	43.891ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.989m	138.746ms	50	50	100.00
V2	executable	sram_ctrl_executable	32.905m	124.831ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.734m	1.019ms	50	50	100.00
		sram_ctrl_partial_access_b2b	11.150m	28.209ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.739m	12.750ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.742m	839.168us	50	50	100.00
V2	regwen	sram_ctrl_regwen	32.729m	4.653ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.580s	4.204ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.443h	239.224ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	0.710s	40.586us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.870s	627.406us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.870s	627.406us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.730s	44.197us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	81.850us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	17.133us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.870s	161.476us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.730s	44.197us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	81.850us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	17.133us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.870s	161.476us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	57.060s	8.112ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.920s	2.101ms	5	5	100.00
		sram_ctrl_tl_intg_err	2.770s	357.090us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.920s	2.101ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.770s	357.090us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	32.729m	4.653ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.740s	81.850us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	32.905m	124.831ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	32.905m	124.831ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	32.905m	124.831ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.989m	138.746ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	57.060s	8.112ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.779m	1.057ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.779m	1.057ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.779m	1.057ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	32.905m	124.831ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.920s	2.101ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.989m	138.746ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.920s	2.101ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.920s	2.101ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.779m	1.057ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.920s	2.101ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.068m	11.313ms	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			1035	1040	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 2 failures.
  - 30.sram_ctrl_stress_all_with_rand_reset.112780391135959183300958202199930047930611353566413790745340720120869548097903
    Line 325, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10570004488 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10570004488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.sram_ctrl_stress_all_with_rand_reset.12701714145839127434690810774888832720691441709138748302088131331830263901617
    Line 293, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/36.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9441285773 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9441285773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job sram_ctrl_main-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 7.sram_ctrl_stress_all.27125551819818529730412078113020138868143693018522269704465532322310294925688
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_all/latest/run.log
```
  Job ID: smart:dd13890d-3418-47ad-a9f4-2da6af592d5b
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test sram_ctrl_bijection has 1 failures.
  - 16.sram_ctrl_bijection.40495251296763080893146728256201558716772196237040570268888411671983357835058
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:755) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 28.sram_ctrl_stress_all_with_rand_reset.80730075129892000797969940610055822735275419148840229699841448503530358570021
    Line 288, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 156521856 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 156521856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/MAIN Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c8985d6745`