SRAM_CTRL/MAIN Simulation Results

Wednesday August 07 2024 23:02:33 UTC

GitHub Revision: bbf435ceff

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6888687353677204195542416712589698377810102273194685652880785004967849651007

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.651m	6.785ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.700s	40.454us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.730s	13.177us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.390s	172.389us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.800s	38.256us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.780s	392.675us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.730s	13.177us	20	20	100.00
		sram_ctrl_csr_aliasing	0.800s	38.256us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.827m	138.163ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.202m	82.966ms	49	50	98.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	26.440m	13.754ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.741m	25.759ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	49.344m	143.409ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	34.812m	39.720ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.773m	187.850ms	50	50	100.00
V2	executable	sram_ctrl_executable	43.508m	94.983ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.843m	4.851ms	50	50	100.00
		sram_ctrl_partial_access_b2b	11.400m	26.611ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.992m	808.686us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.881m	3.263ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	31.401m	14.575ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.390s	2.113ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.884h	2.369s	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	0.770s	18.628us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.340s	147.399us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.340s	147.399us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.700s	40.454us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	13.177us	20	20	100.00
		sram_ctrl_csr_aliasing	0.800s	38.256us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.850s	34.452us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.700s	40.454us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	13.177us	20	20	100.00
		sram_ctrl_csr_aliasing	0.800s	38.256us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.850s	34.452us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.147m	100.741ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.050s	657.254us	5	5	100.00
		sram_ctrl_tl_intg_err	2.790s	404.014us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.050s	657.254us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.790s	404.014us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	31.401m	14.575ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.730s	13.177us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	43.508m	94.983ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	43.508m	94.983ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	43.508m	94.983ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.773m	187.850ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.147m	100.741ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.651m	6.785ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.651m	6.785ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.651m	6.785ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	43.508m	94.983ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.050s	657.254us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.773m	187.850ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.050s	657.254us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.050s	657.254us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.651m	6.785ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.050s	657.254us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.251m	19.514ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1036	1040	99.62

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 1 failures.

    • 4.sram_ctrl_stress_all_with_rand_reset.35568175767558813718318884480625094737155664488057258121154129771066414353190
      Line 312, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 19514427824 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 19514427824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '((pend_req[*].pend == *'b0) || $test$plusargs("disable_assert_final_checks"))' has 1 failures:

  • Test sram_ctrl_mem_partial_access has 1 failures.

    • 14.sram_ctrl_mem_partial_access.95277814838329521903859236694764697211807833102111600717063481434792512346412
      Line 306, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_mem_partial_access/latest/run.log

            Offending '((pend_req[173].pend == 1'b0) || $test$plusargs("disable_assert_final_checks"))'
        UVM_ERROR @ 5182142825 ps: (tlul_assert.sv:301) [ASSERT FAILED] noOutstandingReqsAtEndOfSim_A
        UVM_INFO @ 5182142825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:264) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_regwen has 1 failures.

    • 37.sram_ctrl_regwen.53435732500570078667905192443331275785543190238279807240015328365928275542408
      Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/37.sram_ctrl_regwen/latest/run.log

        UVM_FATAL @ 23179539146 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xce21afb3
        UVM_INFO @ 23179539146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test sram_ctrl_bijection has 1 failures.

    • 39.sram_ctrl_bijection.5728930518459481706375279624692284558232733052525457696855167177015357472307
      Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/39.sram_ctrl_bijection/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.07_09.11.15
• 2024.08.06_09.40.05
• 2024.08.05_11.11.01
• 2024.08.04_06.58.43
• 2024.08.03_09.10.27
• 2024.08.02_08.22.50
• 2024.08.01_09.50.08