SRAM_CTRL/MAIN Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: 3707c48f56

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.441m	470.474us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.730s	75.123us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.740s	12.170us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.190s	301.402us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.750s	22.020us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.510s	2.462ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.740s	12.170us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	22.020us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.106m	82.650ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.089m	82.747ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	29.511m	29.709ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	8.524m	10.718ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	48.134m	749.873ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	28.859m	78.872ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.771m	273.340ms	50	50	100.00
V2	executable	sram_ctrl_executable	34.848m	366.888ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.793m	1.331ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.751m	88.446ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.817m	1.530ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.494m	1.628ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	27.375m	26.186ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.870s	4.810ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.856h	543.049ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	0.740s	81.673us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.580s	280.680us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.580s	280.680us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.730s	75.123us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	12.170us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	22.020us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.890s	150.848us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.730s	75.123us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	12.170us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	22.020us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.890s	150.848us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.060m	43.975ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.400s	1.250ms	5	5	100.00
		sram_ctrl_tl_intg_err	2.440s	375.969us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.400s	1.250ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.440s	375.969us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	27.375m	26.186ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.740s	12.170us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	34.848m	366.888ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	34.848m	366.888ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	34.848m	366.888ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.771m	273.340ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.060m	43.975ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.441m	470.474us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.441m	470.474us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.441m	470.474us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	34.848m	366.888ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.400s	1.250ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.771m	273.340ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.400s	1.250ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.400s	1.250ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.441m	470.474us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.400s	1.250ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.095m	1.874ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1038	1040	99.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

• Job sram_ctrl_main-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test sram_ctrl_stress_all has 1 failures.

    • 21.sram_ctrl_stress_all.13546067337059900540969268124337912849546037804775117788999301598352112239618
      Log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_all/latest/run.log

        Job ID: smart:e95ef5d2-547b-44d4-9755-5f17c83ee5b3
      

• UVM_FATAL (cip_base_vseq.sv:264) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_executable has 1 failures.

    • 36.sram_ctrl_executable.36796677918255856294089554817826861510504978281205199890804899610776822623802
      Line 292, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/36.sram_ctrl_executable/latest/run.log

        UVM_FATAL @ 116103750478 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x8a07eb99
        UVM_INFO @ 116103750478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.08_09.17.36
• 2024.08.07_09.11.15
• 2024.08.06_09.40.05
• 2024.08.05_11.11.01
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