SRAM_CTRL/MAIN Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.446m	481.758us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.790s	38.375us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.730s	23.000us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.880s	186.194us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.780s	41.970us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.730s	359.480us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.730s	23.000us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	41.970us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.551m	39.786ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.068m	5.411ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	35.193m	49.734ms	48	50	96.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.611m	28.606ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	46.611m	172.441ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	38.813m	28.217ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.590m	172.358ms	50	50	100.00
V2	executable	sram_ctrl_executable	34.233m	20.673ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.045m	542.560us	50	50	100.00
		sram_ctrl_partial_access_b2b	10.138m	53.962ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.815m	5.882ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.309m	1.597ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	44.841m	17.475ms	48	50	96.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.990s	3.708ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.571h	971.339ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	0.790s	34.008us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.230s	161.166us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.230s	161.166us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.790s	38.375us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	23.000us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	41.970us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	22.500us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.790s	38.375us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	23.000us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	41.970us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	22.500us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.018m	28.197ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.740s	1.476ms	5	5	100.00
		sram_ctrl_tl_intg_err	2.670s	520.252us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.740s	1.476ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.670s	520.252us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	44.841m	17.475ms	48	50	96.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.730s	23.000us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	34.233m	20.673ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	34.233m	20.673ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	34.233m	20.673ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.590m	172.358ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.018m	28.197ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.446m	481.758us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.446m	481.758us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.446m	481.758us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	34.233m	20.673ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.740s	1.476ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.590m	172.358ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.740s	1.476ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.740s	1.476ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.446m	481.758us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.740s	1.476ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.941m	10.273ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			1033	1040	99.33

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

UVM_FATAL (cip_base_vseq.sv:264) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_regwen has 2 failures.
  - 4.sram_ctrl_regwen.111200359587835725158852133091746313006540210663451606373547076647756177032062
    Line 341, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 198088604441 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x849f40d9
  UVM_INFO @ 198088604441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.sram_ctrl_regwen.88523613324963232520951995299505478083876974411650348837949879134251345315924
    Line 282, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/41.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 44049221428 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x745ea5b5
  UVM_INFO @ 44049221428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:836) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 2 failures.
  - 8.sram_ctrl_stress_all_with_rand_reset.95344862144882756821784427018676415077734404241694816159909794412168571327634
    Line 314, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2254937555 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2254937555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.sram_ctrl_stress_all_with_rand_reset.105001011509258065553636165461187186559736170030232441747674165711561977368913
    Line 313, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8431842152 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8431842152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:264) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_multiple_keys has 2 failures.
  - 14.sram_ctrl_multiple_keys.45374366076856808996450119760339059502486015856088194816695057771904660899211
    Line 290, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 116741983204 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xfc94072b
  UVM_INFO @ 116741983204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.sram_ctrl_multiple_keys.93516499364945433735376737886908928445283317540434106608124269215389815528788
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 23184567926 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xdb89d354
  UVM_INFO @ 23184567926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(rdata_o))' has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 37.sram_ctrl_stress_all.76169017687414023500693508018020169349733261647327696071906007651081694581571
    Line 282, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/37.sram_ctrl_stress_all/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @ 750344816 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @ 750344816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/MAIN Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `07b417ef03`