SRAM_CTRL/MAIN Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.780m	2.531ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.700s	39.241us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.740s	65.479us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.390s	715.618us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.760s	20.976us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.640s	2.153ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.740s	65.479us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	20.976us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.329m	41.362ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.031m	5.781ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	27.316m	19.583ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.548m	13.148ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	49.734m	661.881ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	30.554m	80.330ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.178m	66.111ms	50	50	100.00
V2	executable	sram_ctrl_executable	29.216m	102.161ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.796m	4.002ms	50	50	100.00
		sram_ctrl_partial_access_b2b	11.955m	117.923ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.777m	3.209ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.537m	1.377ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	30.295m	108.122ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.190s	5.576ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.990h	754.697ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	0.740s	36.667us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.130s	153.753us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.130s	153.753us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.700s	39.241us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	65.479us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	20.976us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.850s	185.954us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.700s	39.241us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	65.479us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	20.976us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.850s	185.954us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.030m	25.152ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	4.580s	874.389us	5	5	100.00
		sram_ctrl_tl_intg_err	2.740s	270.484us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	4.580s	874.389us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.740s	270.484us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	30.295m	108.122ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.740s	65.479us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	29.216m	102.161ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	29.216m	102.161ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	29.216m	102.161ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.178m	66.111ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.030m	25.152ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.780m	2.531ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.780m	2.531ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.780m	2.531ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	29.216m	102.161ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	4.580s	874.389us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.178m	66.111ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	4.580s	874.389us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	4.580s	874.389us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.780m	2.531ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	4.580s	874.389us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.196m	6.096ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1037	1040	99.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.94	99.19	94.27	99.72	100.00	96.03	99.12	97.26

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:264) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_multiple_keys has 1 failures.

    • 3.sram_ctrl_multiple_keys.111646979558589114738682939582090311141527231380200489455988226088116826471127
      Line 302, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_multiple_keys/latest/run.log

        UVM_FATAL @ 165986325915 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x82629614
        UVM_INFO @ 165986325915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:264) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_executable has 1 failures.

    • 21.sram_ctrl_executable.41744425017285025165776172624893876884967366975918169790281393658314611606047
      Line 284, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/21.sram_ctrl_executable/latest/run.log

        UVM_FATAL @ 52502172227 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xbbdf9aa1
        UVM_INFO @ 52502172227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:836) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 1 failures.

    • 25.sram_ctrl_stress_all_with_rand_reset.92223967272603160328544544769630421668184616913922374340367314780639569394387
      Line 296, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1017034735 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1017034735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.10_08.34.00
• 2024.08.09_08.03.48
• 2024.08.08_09.17.36
• 2024.08.07_09.11.15
• 2024.08.06_09.40.05
• 2024.08.05_11.11.01
• 2024.08.04_06.58.43