SRAM_CTRL/MAIN Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.587m	1.922ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.730s	52.967us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.700s	31.814us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.320s	307.263us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.770s	70.556us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.640s	1.264ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.700s	31.814us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	70.556us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.873m	197.487ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.996m	22.499ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	42.687m	154.537ms	48	50	96.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.638m	6.132ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	50.128m	615.582ms	47	50	94.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	35.690m	40.458ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.531m	246.850ms	50	50	100.00
V2	executable	sram_ctrl_executable	36.115m	31.172ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.859m	3.606ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.194m	48.860ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.804m	1.706ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.795m	1.368ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	32.760m	53.805ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.350s	3.719ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.577h	4.112s	48	50	96.00
V2	alert_test	sram_ctrl_alert_test	0.720s	18.048us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.700s	247.339us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.700s	247.339us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.730s	52.967us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	31.814us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	70.556us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	18.528us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.730s	52.967us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	31.814us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	70.556us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	18.528us	20	20	100.00
V2		TOTAL			733	740	99.05
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	54.570s	28.322ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	4.420s	909.370us	5	5	100.00
		sram_ctrl_tl_intg_err	2.490s	262.872us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	4.420s	909.370us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.490s	262.872us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	32.760m	53.805ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.700s	31.814us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	36.115m	31.172ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	36.115m	31.172ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	36.115m	31.172ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.531m	246.850ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	54.570s	28.322ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.587m	1.922ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.587m	1.922ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.587m	1.922ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	36.115m	31.172ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	4.420s	909.370us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.531m	246.850ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	4.420s	909.370us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	4.420s	909.370us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.587m	1.922ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	4.420s	909.370us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	6.812m	12.005ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1033	1040	99.33

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

UVM_FATAL (cip_base_vseq.sv:264) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 3 failures:
- Test sram_ctrl_multiple_keys has 2 failures.
  - 7.sram_ctrl_multiple_keys.93281439520669073678117686206442455857886328294904844905006067318486467138284
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 43329781268 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x366d4b26
  UVM_INFO @ 43329781268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.sram_ctrl_multiple_keys.113092197283921433340606661651114264896489652710455609698937444516104409701362
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 29565794475 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x1721ef74
  UVM_INFO @ 29565794475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sram_ctrl_stress_all has 1 failures.
  - 14.sram_ctrl_stress_all.114749043469290283373740349434226528278365330842539412226781807522065624481390
    Line 287, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 2014912817948 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x15f697e8
  UVM_INFO @ 2014912817948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test sram_ctrl_bijection has 3 failures.
  - 24.sram_ctrl_bijection.41460109377766698093542560922221576689299646077993266151306621283069492477812
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/24.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.sram_ctrl_bijection.13620622525476215222132853733805223117019687622676161956470962768028929665805
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/27.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (cip_base_vseq.sv:264) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 21.sram_ctrl_stress_all.61122181067996267342647761644281700051739909695941656113078651133465489241861
    Line 284, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 788866563820 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x1adce970
  UVM_INFO @ 788866563820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/MAIN Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `07b417ef03`