SRAM_CTRL/MAIN Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: c082b8981f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.577m	2.857ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.710s	22.023us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.720s	32.114us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.500s	2.801ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.740s	67.712us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.000s	371.772us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.720s	32.114us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	67.712us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.292m	89.921ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.313m	64.438ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	36.199m	29.852ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.180m	7.339ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	48.430m	792.944ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	33.129m	19.645ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.868m	64.232ms	50	50	100.00
V2	executable	sram_ctrl_executable	35.109m	20.079ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.818m	525.588us	50	50	100.00
		sram_ctrl_partial_access_b2b	11.507m	29.498ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.856m	6.928ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.840m	784.726us	50	50	100.00
V2	regwen	sram_ctrl_regwen	35.047m	97.628ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.600s	6.711ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.912h	377.317ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	0.710s	36.146us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.870s	626.915us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.870s	626.915us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.710s	22.023us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	32.114us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	67.712us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	103.512us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.710s	22.023us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	32.114us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	67.712us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	103.512us	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.385m	88.049ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.570s	1.074ms	5	5	100.00
		sram_ctrl_tl_intg_err	2.780s	407.002us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.570s	1.074ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.780s	407.002us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	35.047m	97.628ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.720s	32.114us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	35.109m	20.079ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	35.109m	20.079ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	35.109m	20.079ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.868m	64.232ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.385m	88.049ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.577m	2.857ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.577m	2.857ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.577m	2.857ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	35.109m	20.079ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.570s	1.074ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.868m	64.232ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.570s	1.074ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.570s	1.074ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.577m	2.857ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.570s	1.074ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.719m	2.960ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1038	1040	99.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	15	93.75
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_regwen has 1 failures.

    • 26.sram_ctrl_regwen.91049166297093456544814282857564893194748102418519389765703412781047844155529
      Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/26.sram_ctrl_regwen/latest/run.log

        UVM_FATAL @ 23205884355 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x89f3814a
        UVM_INFO @ 23205884355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:848) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 1 failures.

    • 28.sram_ctrl_stress_all_with_rand_reset.70108837592488587940811870580026473152199273354715359452607440806270373235458
      Line 313, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2259389593 ps: (cip_base_vseq.sv:848) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2259389593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.12_08.41.59
• 2024.08.11_08.27.52
• 2024.08.10_08.34.00
• 2024.08.09_08.03.48
• 2024.08.08_09.17.36
• 2024.08.07_09.11.15
• 2024.08.06_09.40.05