SRAM_CTRL/MAIN Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: `29d22a60a2`

Branch: os_regression_2024_10_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.873m	3.814ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.960s	51.025us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.080s	24.048us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.140s	679.892us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.080s	22.764us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	7.020s	1.361ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.080s	24.048us	20	20	100.00
		sram_ctrl_csr_aliasing	1.080s	22.764us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	7.672m	42.275ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.686m	40.498ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	32.634m	30.632ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	9.768m	121.518ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	54.648m	169.012ms	47	50	94.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	31.085m	98.067ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.589m	18.243ms	50	50	100.00
V2	executable	sram_ctrl_executable	23.270m	20.784ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.677m	1.898ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.888m	23.143ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.233m	12.690ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.078m	802.976us	50	50	100.00
V2	regwen	sram_ctrl_regwen	23.229m	40.971ms	48	50	96.00
V2	ram_cfg	sram_ctrl_ram_cfg	7.570s	5.611ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.080h	197.679ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.140s	77.205us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	7.760s	473.317us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	7.760s	473.317us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.960s	51.025us	5	5	100.00
		sram_ctrl_csr_rw	1.080s	24.048us	20	20	100.00
		sram_ctrl_csr_aliasing	1.080s	22.764us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.290s	81.502us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.960s	51.025us	5	5	100.00
		sram_ctrl_csr_rw	1.080s	24.048us	20	20	100.00
		sram_ctrl_csr_aliasing	1.080s	22.764us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.290s	81.502us	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.204m	58.648ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	9.550s	1.277ms	5	5	100.00
		sram_ctrl_tl_intg_err	4.400s	2.119ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	9.550s	1.277ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.400s	2.119ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	23.229m	40.971ms	48	50	96.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	23.229m	40.971ms	48	50	96.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.080s	24.048us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	23.270m	20.784ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	23.270m	20.784ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	23.270m	20.784ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.589m	18.243ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.204m	58.648ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	12.790s	8.248ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.873m	3.814ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.873m	3.814ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	23.270m	20.784ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	9.550s	1.277ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.589m	18.243ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	9.550s	1.277ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	9.550s	1.277ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.873m	3.814ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	9.550s	1.277ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.174m	1.206ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1083	1090	99.36

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.64	99.50	96.05	99.72	100.00	97.34	99.13	98.72

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test sram_ctrl_bijection has 3 failures.
  - 25.sram_ctrl_bijection.64682134268651924025963899026948771569892098423126674050186946179237571900842
    Line 83, in log /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.sram_ctrl_bijection.85015893285674187129403221343954457721288057555094730546686168029041239576407
    Line 83, in log /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_regwen has 2 failures.
  - 7.sram_ctrl_regwen.21153439204157233274044207667650018481829880265912395480862653159436611854653
    Line 90, in log /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 23209965102 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xa72e686d
  UVM_INFO @ 23209965102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.sram_ctrl_regwen.64371179541991270793032035334540608762351201112059569944139811276797428982419
    Line 171, in log /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 290612846197 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x9a6d8723
  UVM_INFO @ 290612846197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:867) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 0.sram_ctrl_stress_all_with_rand_reset.103240104645443762887233246494477458389232727195574734517234990849923856987208
    Line 146, in log /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6643110616 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6643110616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 47.sram_ctrl_multiple_keys.37428617270412676923306616361133401106058166909592857761645656036230765808678
    Line 115, in log /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 165433172005 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x37bc6a5c
  UVM_INFO @ 165433172005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/MAIN Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: 29d22a60a2

Branch: os_regression_2024_10_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `29d22a60a2`