SRAM_CTRL/MAIN Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: 78ad89d1aa

Branch: os_regression_2024_09_23

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.126m	1.585ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.800s	34.653us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.060s	71.995us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.040s	155.372us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.790s	56.218us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.910s	6.794ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.060s	71.995us	20	20	100.00
		sram_ctrl_csr_aliasing	0.790s	56.218us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.673m	115.389ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.973m	36.551ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	33.020m	119.422ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	9.226m	6.733ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	46.585m	320.767ms	48	50	96.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	21.925m	22.282ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.887m	17.862ms	50	50	100.00
V2	executable	sram_ctrl_executable	25.610m	22.473ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.919m	3.999ms	50	50	100.00
		sram_ctrl_partial_access_b2b	12.273m	98.215ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.946m	767.857us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.211m	818.964us	50	50	100.00
V2	regwen	sram_ctrl_regwen	30.759m	71.045ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	8.100s	4.785ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.456h	395.727ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	1.200s	142.341us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.010s	161.677us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.010s	161.677us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.800s	34.653us	5	5	100.00
		sram_ctrl_csr_rw	1.060s	71.995us	20	20	100.00
		sram_ctrl_csr_aliasing	0.790s	56.218us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.220s	55.699us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.800s	34.653us	5	5	100.00
		sram_ctrl_csr_rw	1.060s	71.995us	20	20	100.00
		sram_ctrl_csr_aliasing	0.790s	56.218us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.220s	55.699us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.097m	100.335ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	5.400s	854.901us	5	5	100.00
		sram_ctrl_tl_intg_err	2.870s	271.178us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	5.400s	854.901us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.870s	271.178us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	30.759m	71.045ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	30.759m	71.045ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.060s	71.995us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	25.610m	22.473ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	25.610m	22.473ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	25.610m	22.473ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.887m	17.862ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.097m	100.335ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.126m	1.585ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.126m	1.585ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.126m	1.585ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	25.610m	22.473ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	5.400s	854.901us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.887m	17.862ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	5.400s	854.901us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	5.400s	854.901us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.126m	1.585ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	5.400s	854.901us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.547m	9.799ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1037	1040	99.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.30	99.25	95.11	99.72	100.00	96.38	99.13	98.54

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test sram_ctrl_bijection has 1 failures.

    • 21.sram_ctrl_bijection.27566500964741936451771720841080742093253398188602398646769767491055546267793
      Line 83, in log /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/21.sram_ctrl_bijection/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job timed out after * minutes has 1 failures:

  • Test sram_ctrl_bijection has 1 failures.

    • 25.sram_ctrl_bijection.6672368001081188008476773462068247780259815077998371064597204370355428301066
      Log /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/25.sram_ctrl_bijection/latest/run.log

        Job timed out after 60 minutes
      

• UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_stress_all has 1 failures.

    • 31.sram_ctrl_stress_all.67642923863436915791477126269389358351248637356988845898175916104768391363762
      Line 157, in log /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/31.sram_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 310443948863 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x87f915ca
        UVM_INFO @ 310443948863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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